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amdgpu/addrlib: Seperate 2 dcc related workarounds by different flags

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1) dccCompatible for padding MSAA surface to support fast clear
2) dccPipeWorkaround for padding surface to support dcc
This commit is contained in:
Nicolai Hähnle 2016-07-20 10:33:44 +02:00 • committed by Marek Olšák
parent 48bf5d0800
commit a136926eef
3 changed files with 9 additions and 3 deletions
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6
src/amd/addrlib/addrinterface.h
View file

@ -504,7 +504,11 @@ typedef union _ADDR_SURFACE_FLAGS
UINT_32 interleaved : 1; ///< Special flag for interleaved YUV surface padding
UINT_32 tcCompatible : 1; ///< Flag indicates surface needs to be shader readable
UINT_32 dispTileType : 1; ///< NI: force display Tiling for 128 bit shared resoruce
UINT_32 dccCompatible : 1; ///< VI: whether to support dcc fast clear
UINT_32 dccCompatible : 1; ///< VI: whether to make MSAA surface support dcc fast clear
UINT_32 dccPipeWorkaround : 1; ///< VI: whether to workaround the HW limit that
/// dcc can't be enabled if pipe config of tile mode
/// is different from that of ASIC, this flag
/// is address lib internal flag, client should ignore it
UINT_32 czDispCompatible : 1; ///< SI+: CZ family has a HW bug needs special alignment.
/// This flag indicates we need to follow the
/// alignment with CZ families or other ASICs under

2
src/amd/addrlib/core/addrlib1.cpp
View file

@ -336,6 +336,8 @@ ADDR_E_RETURNCODE Lib::ComputeSurfaceInfo(
if (returnCode == ADDR_OK)
{
localIn.flags.dccPipeWorkaround = localIn.flags.dccCompatible;
if (localIn.tileMode == ADDR_TM_UNKNOWN)
{
// HWL layer may override tile mode if necessary

4
src/amd/addrlib/r800/ciaddrlib.cpp
View file

@ -979,7 +979,7 @@ VOID CiLib::HwlOptimizeTileMode(
if (pInOut->maxBaseAlign != 0)
{
pInOut->flags.dccCompatible = FALSE;
pInOut->flags.dccPipeWorkaround = FALSE;
}
}
@ -2095,7 +2095,7 @@ VOID CiLib::HwlComputeSurfaceAlignmentsMacroTiled(
// P4. In theory, all asics that have such switching should be patched but we now only know what
// to pad for Fiji.
if ((m_settings.isFiji == TRUE) &&
(flags.dccCompatible == TRUE) &&
(flags.dccPipeWorkaround == TRUE) &&
(flags.prt == FALSE) &&
(mipLevel == 0) &&
(tileMode == ADDR_TM_PRT_TILED_THIN1) &&