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amd/addrlib: second update for Vega10 + bug fixes

Browse source 
Highlights:
- Display needs tiled pitch alignment to be at least 32 pixels
- Implement Addr2ComputeDccAddrFromCoord().
- Macro-pixel packed formats don't support Z swizzle modes
- Pad pitch and base alignment of PRT + TEX1D to 64KB.
- Fix support for multimedia formats
- Fix a case "PRT" entries are not selected on SI.
- Fix wrong upper bits in equations for 3D resource.
- We can't support 2d array slice rotation in gfx8 swizzle pattern
- Set base alignment for PRT + non-xor swizzle mode resource to 64KB.
- Bug workaround for Z16 4x/8x and Z32 2x/4x/8x MSAA depth texture
- Add stereo support
- Optimize swizzle mode selection
- Report pitch and height in pixels for each mip
- Adjust bpp/expandX for format ADDR_FMT_GB_GR/ADDR_FMT_BG_RG
- Correct tcCompatible flag output for mipmap surface
- Other fixes and cleanups

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák 2017-02-27 22:25:44 +01:00
parent 3e7d62a774
commit 18e760346a
17 changed files with 3312 additions and 2146 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

90
src/amd/addrlib/addrinterface.cpp
View file

@ -1527,6 +1527,38 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeDccInfo(
return returnCode;
}
/**
****************************************************************************************************
* Addr2ComputeDccAddrFromCoord
*
* @brief
* Compute DCC key address according to coordinates
*
* @return
* ADDR_OK if successful, otherwise an error code of ADDR_E_RETURNCODE
****************************************************************************************************
*/
ADDR_E_RETURNCODE ADDR_API Addr2ComputeDccAddrFromCoord(
ADDR_HANDLE hLib, ///< address lib handle
const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn, ///< [in] Dcc info and coordinates
ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut) ///< [out] Dcc address
{
V2::Lib* pLib = V2::Lib::GetLib(hLib);
ADDR_E_RETURNCODE returnCode = ADDR_OK;
if (pLib != NULL)
{
returnCode = pLib->ComputeDccAddrFromCoord(pIn, pOut);
}
else
{
returnCode = ADDR_ERROR;
}
return returnCode;
}
/**
****************************************************************************************************
* Addr2ComputePipeBankXor
@ -1556,6 +1588,64 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputePipeBankXor(
return returnCode;
}
/**
****************************************************************************************************
* Addr2ComputeSlicePipeBankXor
*
* @brief
* Calculate slice pipe bank xor value based on base pipe bank xor and slice id.
****************************************************************************************************
*/
ADDR_E_RETURNCODE ADDR_API Addr2ComputeSlicePipeBankXor(
ADDR_HANDLE hLib, ///< handle of addrlib
const ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT* pIn, ///< [in] input
ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT* pOut) ///< [out] output
{
ADDR_E_RETURNCODE returnCode;
V2::Lib* pLib = V2::Lib::GetLib(hLib);
if (pLib != NULL)
{
returnCode = pLib->ComputeSlicePipeBankXor(pIn, pOut);
}
else
{
returnCode = ADDR_ERROR;
}
return returnCode;
}
/**
****************************************************************************************************
* Addr2ComputeSubResourceOffsetForSwizzlePattern
*
* @brief
* Calculate sub resource offset for swizzle pattern.
****************************************************************************************************
*/
ADDR_E_RETURNCODE ADDR_API Addr2ComputeSubResourceOffsetForSwizzlePattern(
ADDR_HANDLE hLib, ///< handle of addrlib
const ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT* pIn, ///< [in] input
ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT* pOut) ///< [out] output
{
ADDR_E_RETURNCODE returnCode;
V2::Lib* pLib = V2::Lib::GetLib(hLib);
if (pLib != NULL)
{
returnCode = pLib->ComputeSubResourceOffsetForSwizzlePattern(pIn, pOut);
}
else
{
returnCode = ADDR_ERROR;
}
return returnCode;
}
/**
****************************************************************************************************
* Addr2GetPreferredSurfaceSetting

215
src/amd/addrlib/addrinterface.h
View file

@ -2427,14 +2427,17 @@ typedef struct _ADDR2_MIP_INFO
UINT_32 pitch; ///< Pitch in elements
UINT_32 height; ///< Padded height in elements
UINT_32 depth; ///< Padded depth
UINT_32 offset; ///< Offset in bytes from mip base
UINT_32 pixelPitch; ///< Pitch in pixels
UINT_32 pixelHeight; ///< Padded height in pixels
UINT_32 equationIndex; ///< Equation index in the equation table
UINT_32 mipOffsetXBytes; ///< Mip start position offset in byte in X direction
UINT_32 mipOffsetYPixel; ///< Mip start position offset in pixel in Y direction
UINT_32 mipOffsetZPixel; ///< Mip start position offset in pixel in Z direction
UINT_32 postSwizzleOffset; ///< Offset which is used to be added directly onto
/// the address calculated by equation
UINT_64 offset; ///< Offset in bytes from mip base, should only be used
///< to setup vam surface descriptor, can't be used
///< to setup swizzle pattern
UINT_64 macroBlockOffset; ///< macro block offset in bytes from mip base
UINT_32 mipTailOffset; ///< mip tail offset in bytes
UINT_32 mipTailCoordX; ///< mip tail coord x
UINT_32 mipTailCoordY; ///< mip tail coord y
UINT_32 mipTailCoordZ; ///< mip tail coord z
} ADDR2_MIP_INFO;
/**
@ -2459,7 +2462,7 @@ typedef struct _ADDR2_COMPUTE_SURFACE_INFO_OUTPUT
UINT_32 mipChainPitch; ///< Pitch (of total mip chain) in elements
UINT_32 mipChainHeight; ///< Padded height (of total mip chain) in elements
UINT_32 mipChainSlice; ///< Padded depth (of total mip chain)
UINT_32 sliceSize; ///< Slice (total mip chain) size in bytes
UINT_64 sliceSize; ///< Slice (total mip chain) size in bytes
UINT_64 surfSize; ///< Surface (total mip chain) size in bytes
UINT_32 baseAlign; ///< Base address alignment
UINT_32 bpp; ///< Bits per elements
@ -2485,7 +2488,9 @@ typedef struct _ADDR2_COMPUTE_SURFACE_INFO_OUTPUT
/// contain numMipLevels entries
UINT_32 equationIndex; ///< Equation index in the equation table of mip0
BOOL_32 firstMipInTail; ///< If whole mipchain falls into mip tail block
BOOL_32 mipChainInTail; ///< If whole mipchain falls into mip tail block
UINT_32 firstMipIdInTail; ///< The id of first mip in tail, if there is no mip
/// in tail, it will be set to number of mip levels
} ADDR2_COMPUTE_SURFACE_INFO_OUTPUT;
/**
@ -2674,12 +2679,26 @@ typedef union _ADDR2_META_FLAGS
typedef struct _ADDR2_META_MIP_INFO
{
BOOL_32 inMiptail;
UINT_32 startX;
UINT_32 startY;
UINT_32 startZ;
UINT_32 width;
UINT_32 height;
UINT_32 depth;
union
{
struct
{
UINT_32 startX;
UINT_32 startY;
UINT_32 startZ;
UINT_32 width;
UINT_32 height;
UINT_32 depth;
};
struct
{
UINT_32 offset; ///< metadata offset within one slice,
/// the thickness of a slice is meta block depth.
UINT_32 sliceSize; ///< metadata size within one slice,
/// the thickness of a slice is meta block depth.
};
};
} ADDR2_META_MIP_INFO;
/**
@ -2701,6 +2720,9 @@ typedef struct _ADDR2_COMPUTE_HTILE_INFO_INPUT
UINT_32 unalignedHeight; ///< Depth surface original height (of mip0)
UINT_32 numSlices; ///< Number of slices of depth surface (of mip0)
UINT_32 numMipLevels; ///< Total mipmap levels of color surface
UINT_32 firstMipIdInTail; ///< id of the first mip in tail,
/// if no mip is in tail, it should be set to
/// number of mip levels
} ADDR2_COMPUTE_HTILE_INFO_INPUT;
/**
@ -3160,8 +3182,8 @@ typedef struct _ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT
UINT_32 unalignedHeight; ///< Color surface original height
UINT_32 numSamples; ///< Number of samples
UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as
/// number of samples for normal AA; Set it to the
/// number of fragments for EQAA
/// number of samples for normal AA; Set it to the
/// number of fragments for EQAA
UINT_32 tileSwizzle; ///< Combined swizzle used to do bank/pipe rotation
ADDR2_FMASK_FLAGS fMaskFlags; ///< FMASK flags
@ -3286,6 +3308,8 @@ typedef struct _ADDR2_COMPUTE_DCCINFO_INPUT
UINT_32 numMipLevels; ///< Total mipmap levels of color surface
UINT_32 dataSurfaceSize; ///< The padded size of all slices and mip levels
///< useful in meta linear case
UINT_32 firstMipIdInTail; ///< The id of first mip in tail, if no mip is in tail,
/// it should be number of mip levels
} ADDR2_COMPUTE_DCCINFO_INPUT;
/**
@ -3336,6 +3360,66 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputeDccInfo(
ADDR2_COMPUTE_DCCINFO_OUTPUT* pOut);
/**
****************************************************************************************************
* ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT
*
* @brief
* Input structure for Addr2ComputeDccAddrFromCoord
*
****************************************************************************************************
*/
typedef struct _ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT
{
UINT_32 size; ///< Size of this structure in bytes
UINT_32 x; ///< X coordinate
UINT_32 y; ///< Y coordinate
UINT_32 slice; ///< Index of slices
UINT_32 sample; ///< Index of samples, means fragment index for EQAA
UINT_32 mipId; ///< mipmap level id
ADDR2_META_FLAGS dccKeyFlags; ///< DCC flags
ADDR2_SURFACE_FLAGS colorFlags; ///< Color surface flags
AddrResourceType resourceType; ///< Color surface type
AddrSwizzleMode swizzleMode; ///< Color surface swizzle mode
UINT_32 bpp; ///< Color surface bits per pixel
UINT_32 unalignedWidth; ///< Color surface original width (of mip0)
UINT_32 unalignedHeight; ///< Color surface original height (of mip0)
UINT_32 numSlices; ///< Color surface original slices (of mip0)
UINT_32 numMipLevels; ///< Color surface mipmap levels
UINT_32 numFrags; ///< Color surface fragment number
UINT_32 pipeXor; ///< pipe Xor setting
} ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT;
/**
****************************************************************************************************
* ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT
*
* @brief
* Output structure for Addr2ComputeDccAddrFromCoord
****************************************************************************************************
*/
typedef struct _ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT
{
UINT_32 size; ///< Size of this structure in bytes
UINT_64 addr; ///< DCC address in bytes
} ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT;
/**
****************************************************************************************************
* Addr2ComputeDccAddrFromCoord
*
* @brief
* Compute DCC address according to coordinates (of MSAA color buffer)
****************************************************************************************************
*/
ADDR_E_RETURNCODE ADDR_API Addr2ComputeDccAddrFromCoord(
ADDR_HANDLE hLib,
const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn,
ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut);
////////////////////////////////////////////////////////////////////////////////////////////////////
// Misc functions for Gfx9
@ -3356,6 +3440,11 @@ typedef struct _ADDR2_COMPUTE_PIPEBANKXOR_INPUT
ADDR2_SURFACE_FLAGS flags; ///< Surface flag
AddrSwizzleMode swizzleMode; ///< Surface swizzle mode
AddrResourceType resourceType; ///< Surface resource type
AddrFormat format; ///< Surface format
UINT_32 numSamples; ///< Number of samples
UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as
/// number of samples for normal AA; Set it to the
/// number of fragments for EQAA
} ADDR2_COMPUTE_PIPEBANKXOR_INPUT;
/**
@ -3385,7 +3474,97 @@ ADDR_E_RETURNCODE ADDR_API Addr2ComputePipeBankXor(
const ADDR2_COMPUTE_PIPEBANKXOR_INPUT* pIn,
ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT* pOut);
/**
****************************************************************************************************
* ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT
*
* @brief
* Input structure of Addr2ComputeSlicePipeBankXor
****************************************************************************************************
*/
typedef struct _ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT
{
UINT_32 size; ///< Size of this structure in bytes
AddrSwizzleMode swizzleMode; ///< Surface swizzle mode
AddrResourceType resourceType; ///< Surface resource type
UINT_32 basePipeBankXor; ///< Base pipe bank xor
UINT_32 slice; ///< Slice id
UINT_32 numSamples; ///< Number of samples
} ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT;
/**
****************************************************************************************************
* ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT
*
* @brief
* Output structure of Addr2ComputeSlicePipeBankXor
****************************************************************************************************
*/
typedef struct _ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT
{
UINT_32 size; ///< Size of this structure in bytes
UINT_32 pipeBankXor; ///< Pipe bank xor
} ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT;
/**
****************************************************************************************************
* Addr2ComputeSlicePipeBankXor
*
* @brief
* Calculate slice pipe bank xor value based on base pipe bank xor and slice id.
****************************************************************************************************
*/
ADDR_E_RETURNCODE ADDR_API Addr2ComputeSlicePipeBankXor(
ADDR_HANDLE hLib,
const ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT* pIn,
ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT* pOut);
/**
****************************************************************************************************
* ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT
*
* @brief
* Input structure of Addr2ComputeSubResourceOffsetForSwizzlePattern
****************************************************************************************************
*/
typedef struct _ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT
{
UINT_32 size; ///< Size of this structure in bytes
AddrSwizzleMode swizzleMode; ///< Surface swizzle mode
AddrResourceType resourceType; ///< Surface resource type
UINT_32 pipeBankXor; ///< Per resource xor
UINT_32 slice; ///< Slice id
UINT_64 sliceSize; ///< Slice size of a mip chain
UINT_64 macroBlockOffset; ///< Macro block offset, returned in ADDR2_MIP_INFO
UINT_32 mipTailOffset; ///< Mip tail offset, returned in ADDR2_MIP_INFO
} ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT;
/**
****************************************************************************************************
* ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT
*
* @brief
* Output structure of Addr2ComputeSubResourceOffsetForSwizzlePattern
****************************************************************************************************
*/
typedef struct _ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT
{
UINT_32 size; ///< Size of this structure in bytes
UINT_64 offset; ///< offset
} ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT;
/**
****************************************************************************************************
* Addr2ComputeSubResourceOffsetForSwizzlePattern
*
* @brief
* Calculate sub resource offset to support swizzle pattern.
****************************************************************************************************
*/
ADDR_E_RETURNCODE ADDR_API Addr2ComputeSubResourceOffsetForSwizzlePattern(
ADDR_HANDLE hLib,
const ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT* pIn,
ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT* pOut);
/**
****************************************************************************************************
@ -3439,6 +3618,8 @@ typedef struct _ADDR2_GET_PREFERRED_SURF_SETTING_INPUT
/// number of samples for normal AA; Set it to the
/// number of fragments for EQAA
UINT_32 maxAlign; ///< maximum base/size alignment requested by client
UINT_32 minSizeAlign; ///< memory allocated for surface in client driver will
/// be padded to multiple of this value (in bytes)
} ADDR2_GET_PREFERRED_SURF_SETTING_INPUT;
/**

52
src/amd/addrlib/core/addrcommon.h
View file

@ -188,6 +188,15 @@ static const INT_32 TileIndexNoMacroIndex = -3;
} // V1
namespace V2
{
////////////////////////////////////////////////////////////////////////////////////////////////////
// Common constants
////////////////////////////////////////////////////////////////////////////////////////////////////
static const UINT_32 MaxSurfaceHeight = 16384;
} // V2
////////////////////////////////////////////////////////////////////////////////////////////////////
// Common macros
////////////////////////////////////////////////////////////////////////////////////////////////////
@ -431,9 +440,7 @@ static inline INT_32 Max(
static inline UINT_32 NextPow2(
UINT_32 dim) ///< [in] dimension of miplevel
{
UINT_32 newDim;
newDim = 1;
UINT_32 newDim = 1;
if (dim > 0x7fffffff)
{
@ -732,7 +739,7 @@ static inline UINT_32 MortonGen3d(
* ReverseBitVector
*
* @brief
* Return reversed lowest num bits of v
* Return reversed lowest num bits of v: v[0]v[1]...v[num-2]v[num-1]
****************************************************************************************************
*/
static inline UINT_32 ReverseBitVector(
@ -860,7 +867,7 @@ static inline VOID InitChannel(
{
pChanDst->valid = pChanSrc->valid;
pChanDst->channel = pChanSrc->channel;
pChanDst->index = pChanSrc->channel;
pChanDst->index = pChanSrc->index;
}
/**
@ -872,9 +879,9 @@ static inline VOID InitChannel(
****************************************************************************************************
*/
static inline UINT_32 GetMaxValidChannelIndex(
ADDR_CHANNEL_SETTING *pChanSet, ///< [in] channel setting to be initialized
UINT_32 searchCount, ///< [in] number of channel setting to be searched
UINT_32 channel) ///< [in] channel to be searched
const ADDR_CHANNEL_SETTING *pChanSet, ///< [in] channel setting to be initialized
UINT_32 searchCount,///< [in] number of channel setting to be searched
UINT_32 channel) ///< [in] channel to be searched
{
UINT_32 index = 0;
@ -889,6 +896,35 @@ static inline UINT_32 GetMaxValidChannelIndex(
return index;
}
/**
****************************************************************************************************
* GetCoordActiveMask
*
* @brief
* Get bit mask which indicates which positions in the equation match the target coord
****************************************************************************************************
*/
static inline UINT_32 GetCoordActiveMask(
const ADDR_CHANNEL_SETTING *pChanSet, ///< [in] channel setting to be initialized
UINT_32 searchCount,///< [in] number of channel setting to be searched
UINT_32 channel, ///< [in] channel to be searched
UINT_32 index) ///< [in] index to be searched
{
UINT_32 mask = 0;
for (UINT_32 i = 0; i < searchCount; i++)
{
if ((pChanSet[i].valid == TRUE) &&
(pChanSet[i].channel == channel) &&
(pChanSet[i].index == index))
{
mask |= (1 << i);
}
}
return mask;
}
} // Addr
#endif // __ADDR_COMMON_H__

60
src/amd/addrlib/core/addrelemlib.cpp
View file

@ -1289,7 +1289,14 @@ VOID ElemLib::RestoreSurfaceInfo(
break;
case ADDR_PACKED_GBGR:
case ADDR_PACKED_BGRG:
originalBits = bpp; // 32-bit packed ==> 2 32-bit result
if (m_pAddrLib->GetChipFamily() >= ADDR_CHIP_FAMILY_AI)
{
originalBits = bpp / expandX;
}
else
{
originalBits = bpp; // 32-bit packed ==> 2 32-bit result
}
break;
case ADDR_PACKED_BC1: // Fall through
case ADDR_PACKED_BC4:
@ -1387,11 +1394,27 @@ UINT_32 ElemLib::GetBitsPerPixel(
break;
case ADDR_FMT_GB_GR: // treat as FMT_8_8
elemMode = ADDR_PACKED_GBGR;
bpp = 16;
if (m_pAddrLib->GetChipFamily() >= ADDR_CHIP_FAMILY_AI)
{
bpp = 32;
expandX = 2;
}
else
{
bpp = 16;
}
break;
case ADDR_FMT_BG_RG: // treat as FMT_8_8
elemMode = ADDR_PACKED_BGRG;
bpp = 16;
if (m_pAddrLib->GetChipFamily() >= ADDR_CHIP_FAMILY_AI)
{
bpp = 32;
expandX = 2;
}
else
{
bpp = 16;
}
break;
case ADDR_FMT_8_8_8_8:
case ADDR_FMT_2_10_10_10:
@ -1804,4 +1827,35 @@ BOOL_32 ElemLib::IsExpand3x(
return is3x;
}
/**
****************************************************************************************************
* ElemLib::IsMacroPixelPacked
*
* @brief
* TRUE if this is a macro-pixel-packed format.
*
* @note
*
* @return
* BOOL_32
****************************************************************************************************
*/
BOOL_32 ElemLib::IsMacroPixelPacked(
AddrFormat format) ///< [in] Format
{
BOOL_32 isMacroPixelPacked = FALSE;
switch (format)
{
case ADDR_FMT_BG_RG:
case ADDR_FMT_GB_GR:
isMacroPixelPacked = TRUE;
break;
default:
break;
}
return isMacroPixelPacked;
}
}

3
src/amd/addrlib/core/addrelemlib.h
View file

@ -216,7 +216,7 @@ public:
AddrDepthFormat format, PixelFormatInfo* pInfo) const;
UINT_32 GetBitsPerPixel(
AddrFormat format, ElemMode* pElemMode,
AddrFormat format, ElemMode* pElemMode = NULL,
UINT_32* pExpandX = NULL, UINT_32* pExpandY = NULL, UINT_32* pBitsUnused = NULL);
static VOID SetClearComps(
@ -245,6 +245,7 @@ public:
static BOOL_32 IsCompressed(AddrFormat format);
static BOOL_32 IsBlockCompressed(AddrFormat format);
static BOOL_32 IsExpand3x(AddrFormat format);
static BOOL_32 IsMacroPixelPacked(AddrFormat format);
protected:

6
src/amd/addrlib/core/addrlib.h
View file

@ -261,9 +261,9 @@ private:
ElemLib* m_pElemLib; ///< Element Lib pointer
};
Lib* SiHwlInit (const Client* pClient);
Lib* CiHwlInit (const Client* pClient);
Lib* Gfx9HwlInit(const Client* pClient);
Lib* SiHwlInit (const Client* pClient);
Lib* CiHwlInit (const Client* pClient);
Lib* Gfx9HwlInit (const Client* pClient);
} // Addr

47
src/amd/addrlib/core/addrlib1.cpp
View file

@ -259,10 +259,9 @@ ADDR_E_RETURNCODE Lib::ComputeSurfaceInfo(
// Also Mip 1+ needs an element pitch of 32 bits so we do not need this workaround
// but we use this flag to skip RestoreSurfaceInfo below
if ((elemMode == ADDR_EXPANDED) &&
(expandX > 1))
if ((elemMode == ADDR_EXPANDED) && (expandX > 1))
{
ADDR_ASSERT(localIn.tileMode == ADDR_TM_LINEAR_ALIGNED || localIn.height == 1);
ADDR_ASSERT(IsLinear(localIn.tileMode));
}
GetElemLib()->AdjustSurfaceInfo(elemMode,
@ -3621,7 +3620,7 @@ VOID Lib::OptimizeTileMode(
{
tileMode = ADDR_TM_LINEAR_ALIGNED;
}
else if (IsMacroTiled(tileMode))
else if (IsMacroTiled(tileMode) && (pInOut->flags.tcCompatible == FALSE))
{
if (DegradeTo1D(width, height, macroWidthAlign, macroHeightAlign))
{
@ -3878,41 +3877,33 @@ UINT_32 Lib::HwlGetPipes(
* @brief
* Get quad buffer stereo information
* @return
* TRUE if no error
* N/A
****************************************************************************************************
*/
BOOL_32 Lib::ComputeQbStereoInfo(
VOID Lib::ComputeQbStereoInfo(
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut ///< [in,out] updated pOut+pStereoInfo
) const
{
BOOL_32 success = FALSE;
ADDR_ASSERT(pOut->bpp >= 8);
ADDR_ASSERT((pOut->surfSize % pOut->baseAlign) == 0);
if (pOut->pStereoInfo)
{
ADDR_ASSERT(pOut->bpp >= 8);
ADDR_ASSERT((pOut->surfSize % pOut->baseAlign) == 0);
// Save original height
pOut->pStereoInfo->eyeHeight = pOut->height;
// Save original height
pOut->pStereoInfo->eyeHeight = pOut->height;
// Right offset
pOut->pStereoInfo->rightOffset = static_cast<UINT_32>(pOut->surfSize);
// Right offset
pOut->pStereoInfo->rightOffset = static_cast<UINT_32>(pOut->surfSize);
pOut->pStereoInfo->rightSwizzle = HwlComputeQbStereoRightSwizzle(pOut);
// Double height
pOut->height <<= 1;
pOut->pixelHeight <<= 1;
pOut->pStereoInfo->rightSwizzle = HwlComputeQbStereoRightSwizzle(pOut);
// Double height
pOut->height <<= 1;
pOut->pixelHeight <<= 1;
// Double size
pOut->surfSize <<= 1;
// Double size
pOut->surfSize <<= 1;
// Right start address meets the base align since it is guaranteed by AddrLib1
// Right start address meets the base align since it is guaranteed by AddrLib1
// 1D surface on SI may break this rule, but we can force it to meet by checking .qbStereo.
success = TRUE;
}
return success;
// 1D surface on SI may break this rule, but we can force it to meet by checking .qbStereo.
}

2
src/amd/addrlib/core/addrlib1.h
View file

@ -496,7 +496,7 @@ protected:
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
/// Quad buffer stereo support, has its implementation in ind. layer
virtual BOOL_32 ComputeQbStereoInfo(
VOID ComputeQbStereoInfo(
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
/// Pure virutual function to compute stereo bank swizzle for right eye

1906
src/amd/addrlib/core/addrlib2.cpp
View file

File diff suppressed because it is too large Load diff

329
src/amd/addrlib/core/addrlib2.h
View file

@ -25,10 +25,10 @@
*/
/**
****************************************************************************************************
************************************************************************************************************************
* @file addrlib2.h
* @brief Contains the Addr::V2::Lib class definition.
****************************************************************************************************
************************************************************************************************************************
*/
#ifndef __ADDR2_LIB2_H__
@ -42,9 +42,9 @@ namespace V2
{
/**
****************************************************************************************************
************************************************************************************************************************
* @brief Flags for SwizzleModeTable
****************************************************************************************************
************************************************************************************************************************
*/
struct SwizzleModeFlags
{
@ -66,6 +66,8 @@ struct SwizzleModeFlags
UINT_32 isXor : 1; // XOR after swizzle if set
UINT_32 isT : 1; // T mode
UINT_32 isRtOpt : 1; // mode opt for render target
};
struct Dim2d
@ -82,9 +84,9 @@ struct Dim3d
};
/**
****************************************************************************************************
************************************************************************************************************************
* @brief This class contains asic independent address lib functionalities
****************************************************************************************************
************************************************************************************************************************
*/
class Lib : public Addr::Lib
{
@ -155,10 +157,22 @@ public:
const ADDR2_COMPUTE_DCCINFO_INPUT* pIn,
ADDR2_COMPUTE_DCCINFO_OUTPUT* pOut) const;
ADDR_E_RETURNCODE ComputeDccAddrFromCoord(
const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn,
ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut) const;
// Misc
ADDR_E_RETURNCODE ComputePipeBankXor(
const ADDR2_COMPUTE_PIPEBANKXOR_INPUT* pIn,
ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT* pOut);
ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT* pOut);
ADDR_E_RETURNCODE ComputeSlicePipeBankXor(
const ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT* pIn,
ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT* pOut);
ADDR_E_RETURNCODE ComputeSubResourceOffsetForSwizzlePattern(
const ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT* pIn,
ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT* pOut);
ADDR_E_RETURNCODE Addr2GetPreferredSurfaceSetting(
const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn,
@ -168,77 +182,77 @@ protected:
Lib(); // Constructor is protected
Lib(const Client* pClient);
static const SwizzleModeFlags SwizzleModeTable[ADDR_SW_MAX_TYPE];
static const UINT_32 MaxNumOfBpp = 5;
static const Dim2d Block256b[];
static const Dim3d Block1kb[];
static const Dim2d Block256_2d[MaxNumOfBpp];
static const Dim3d Block1K_3d[MaxNumOfBpp];
static const Dim2d CompressBlock2d[];
static const Dim3d CompressBlock3dS[];
static const Dim3d CompressBlock3dZ[];
static const UINT_32 MaxMacroBits;
static const UINT_32 MipTailOffset[];
static const UINT_32 PrtAlignment = 64 * 1024;
static const UINT_32 MaxMacroBits = 20;
// Checking block size
static BOOL_32 IsBlock256b(AddrSwizzleMode swizzleMode)
BOOL_32 IsBlock256b(AddrSwizzleMode swizzleMode) const
{
return SwizzleModeTable[swizzleMode].is256b;
return m_swizzleModeTable[swizzleMode].is256b;
}
static BOOL_32 IsBlock4kb(AddrSwizzleMode swizzleMode)
BOOL_32 IsBlock4kb(AddrSwizzleMode swizzleMode) const
{
return SwizzleModeTable[swizzleMode].is4kb;
return m_swizzleModeTable[swizzleMode].is4kb;
}
static BOOL_32 IsBlock64kb(AddrSwizzleMode swizzleMode)
BOOL_32 IsBlock64kb(AddrSwizzleMode swizzleMode) const
{
return SwizzleModeTable[swizzleMode].is64kb;
return m_swizzleModeTable[swizzleMode].is64kb;
}
static BOOL_32 IsBlockVariable(AddrSwizzleMode swizzleMode)
BOOL_32 IsBlockVariable(AddrSwizzleMode swizzleMode) const
{
return SwizzleModeTable[swizzleMode].isVar;
return m_swizzleModeTable[swizzleMode].isVar;
}
// Checking swizzle mode
static BOOL_32 IsLinear(AddrSwizzleMode swizzleMode)
BOOL_32 IsLinear(AddrSwizzleMode swizzleMode) const
{
return SwizzleModeTable[swizzleMode].isLinear;
return m_swizzleModeTable[swizzleMode].isLinear;
}
static BOOL_32 IsZOrderSwizzle(AddrSwizzleMode swizzleMode)
BOOL_32 IsRtOptSwizzle(AddrSwizzleMode swizzleMode) const
{
return SwizzleModeTable[swizzleMode].isZ;
return m_swizzleModeTable[swizzleMode].isRtOpt;
}
static BOOL_32 IsStandardSwizzle(AddrResourceType resourceType, AddrSwizzleMode swizzleMode)
BOOL_32 IsZOrderSwizzle(AddrSwizzleMode swizzleMode) const
{
return SwizzleModeTable[swizzleMode].isStd ||
(IsTex3d(resourceType) && SwizzleModeTable[swizzleMode].isDisp);
return m_swizzleModeTable[swizzleMode].isZ;
}
static BOOL_32 IsDisplaySwizzle(AddrResourceType resourceType, AddrSwizzleMode swizzleMode)
BOOL_32 IsStandardSwizzle(AddrResourceType resourceType, AddrSwizzleMode swizzleMode) const
{
return IsTex2d(resourceType) && SwizzleModeTable[swizzleMode].isDisp;
return HwlIsStandardSwizzle(resourceType, swizzleMode);
}
static BOOL_32 IsRotateSwizzle(AddrSwizzleMode swizzleMode)
BOOL_32 IsDisplaySwizzle(AddrResourceType resourceType, AddrSwizzleMode swizzleMode) const
{
return SwizzleModeTable[swizzleMode].isRot;
return HwlIsDisplaySwizzle(resourceType, swizzleMode);
}
static BOOL_32 IsXor(AddrSwizzleMode swizzleMode)
BOOL_32 IsRotateSwizzle(AddrSwizzleMode swizzleMode) const
{
return SwizzleModeTable[swizzleMode].isXor;
return m_swizzleModeTable[swizzleMode].isRot;
}
static BOOL_32 IsPrt(AddrSwizzleMode swizzleMode)
BOOL_32 IsXor(AddrSwizzleMode swizzleMode) const
{
return SwizzleModeTable[swizzleMode].isT;
return m_swizzleModeTable[swizzleMode].isXor;
}
static BOOL_32 IsNonPrtXor(AddrSwizzleMode swizzleMode)
BOOL_32 IsPrt(AddrSwizzleMode swizzleMode) const
{
return m_swizzleModeTable[swizzleMode].isT;
}
BOOL_32 IsNonPrtXor(AddrSwizzleMode swizzleMode) const
{
return (IsXor(swizzleMode) && (IsPrt(swizzleMode) == FALSE));
}
@ -259,23 +273,21 @@ protected:
return (resourceType == ADDR_RSRC_TEX_3D);
}
static BOOL_32 IsThick(AddrResourceType resourceType, AddrSwizzleMode swizzleMode)
BOOL_32 IsThick(AddrResourceType resourceType, AddrSwizzleMode swizzleMode) const
{
return (IsTex3d(resourceType) &&
(SwizzleModeTable[swizzleMode].isZ || SwizzleModeTable[swizzleMode].isStd));
return HwlIsThick(resourceType, swizzleMode);
}
static BOOL_32 IsThin(AddrResourceType resourceType, AddrSwizzleMode swizzleMode)
BOOL_32 IsThin(AddrResourceType resourceType, AddrSwizzleMode swizzleMode) const
{
return (IsTex2d(resourceType) ||
(IsTex3d(resourceType) && SwizzleModeTable[swizzleMode].isDisp));
return HwlIsThin(resourceType, swizzleMode);
}
UINT_32 GetBlockSizeLog2(AddrSwizzleMode swizzleMode) const
{
UINT_32 blockSizeLog2 = 0;
if (IsBlock256b(swizzleMode))
if (IsBlock256b(swizzleMode) || IsLinear(swizzleMode))
{
blockSizeLog2 = 8;
}
@ -307,7 +319,7 @@ protected:
static UINT_32 GetFmaskBpp(UINT_32 sample, UINT_32 frag)
{
sample = (sample == 0) ? 1 : sample;
frag = (frag == 0) ? sample : frag;
frag = (frag == 0) ? sample : frag;
UINT_32 fmaskBpp = QLog2(frag);
@ -326,6 +338,38 @@ protected:
return fmaskBpp;
}
virtual BOOL_32 HwlIsStandardSwizzle(
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode) const
{
ADDR_NOT_IMPLEMENTED();
return FALSE;
}
virtual BOOL_32 HwlIsDisplaySwizzle(
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode) const
{
ADDR_NOT_IMPLEMENTED();
return FALSE;
}
virtual BOOL_32 HwlIsThin(
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode) const
{
ADDR_NOT_IMPLEMENTED();
return FALSE;
}
virtual BOOL_32 HwlIsThick(
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode) const
{
ADDR_NOT_IMPLEMENTED();
return FALSE;
}
virtual ADDR_E_RETURNCODE HwlComputeHtileInfo(
const ADDR2_COMPUTE_HTILE_INFO_INPUT* pIn,
ADDR2_COMPUTE_HTILE_INFO_OUTPUT* pOut) const
@ -350,6 +394,14 @@ protected:
return ADDR_NOTSUPPORTED;
}
virtual ADDR_E_RETURNCODE HwlComputeDccAddrFromCoord(
const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn,
ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut) const
{
ADDR_NOT_IMPLEMENTED();
return ADDR_NOTSUPPORTED;
}
virtual ADDR_E_RETURNCODE HwlComputeCmaskAddrFromCoord(
const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn,
ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut) const
@ -425,9 +477,60 @@ protected:
return 0;
}
UINT_32 ComputeSurfaceBaseAlign(AddrSwizzleMode swizzleMode) const
virtual ADDR_E_RETURNCODE HwlComputePipeBankXor(
const ADDR2_COMPUTE_PIPEBANKXOR_INPUT* pIn,
ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT* pOut) const
{
return HwlComputeSurfaceBaseAlign(swizzleMode);
ADDR_NOT_IMPLEMENTED();
return ADDR_NOTSUPPORTED;
}
virtual ADDR_E_RETURNCODE HwlComputeSlicePipeBankXor(
const ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT* pIn,
ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT* pOut) const
{
ADDR_NOT_IMPLEMENTED();
return ADDR_NOTSUPPORTED;
}
virtual ADDR_E_RETURNCODE HwlComputeSubResourceOffsetForSwizzlePattern(
const ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT* pIn,
ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT* pOut) const
{
ADDR_NOT_IMPLEMENTED();
return ADDR_NOTSUPPORTED;
}
virtual ADDR_E_RETURNCODE HwlGetPreferredSurfaceSetting(
const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn,
ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT* pOut) const
{
ADDR_NOT_IMPLEMENTED();
return ADDR_NOTSUPPORTED;
}
virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoSanityCheck(
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const
{
ADDR_NOT_IMPLEMENTED();
return ADDR_NOTSUPPORTED;
}
virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoTiled(
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const
{
ADDR_NOT_IMPLEMENTED();
return ADDR_NOTIMPLEMENTED;
}
virtual ADDR_E_RETURNCODE HwlComputeSurfaceAddrFromCoordTiled(
const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const
{
ADDR_NOT_IMPLEMENTED();
return ADDR_NOTIMPLEMENTED;
}
ADDR_E_RETURNCODE ComputeBlock256Equation(
@ -488,13 +591,6 @@ protected:
const _ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn) const;
// Misc
ADDR_E_RETURNCODE ComputeBlockDimensionForSurf(
Dim3d* pDim,
UINT_32 bpp,
UINT_32 numSamples,
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode) const;
ADDR_E_RETURNCODE ComputeBlockDimensionForSurf(
UINT_32* pWidth,
UINT_32* pHeight,
@ -525,26 +621,6 @@ protected:
return static_cast<UINT_64>(pPadDim->w) * pPadDim->h * pPadDim->d;
}
UINT_32 GetMipChainInfo(
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode,
UINT_32 bpp,
UINT_32 mip0Width,
UINT_32 mip0Height,
UINT_32 mip0Depth,
UINT_32 blockWidth,
UINT_32 blockHeight,
UINT_32 blockDepth,
UINT_32 numMipLevel,
ADDR2_MIP_INFO* pMipInfo) const;
VOID GetMetaMiptailInfo(
ADDR2_META_MIP_INFO* pInfo,
Dim3d mipCoord,
UINT_32 numMipInTail,
Dim3d* pMetaBlkDim
) const;
static ADDR_E_RETURNCODE ExtractPipeBankXor(
UINT_32 pipeBankXor,
UINT_32 bankBits,
@ -560,76 +636,6 @@ protected:
return (Max((numSlices >> mipId), 1u) > slice);
}
static AddrMajorMode GetMajorMode(
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode,
UINT_32 mip0WidthInBlk,
UINT_32 mip0HeightInBlk,
UINT_32 mip0DepthInBlk)
{
BOOL_32 yMajor = (mip0WidthInBlk < mip0HeightInBlk);
BOOL_32 xMajor = (yMajor == FALSE);
if (IsThick(resourceType, swizzleMode))
{
yMajor = yMajor && (mip0HeightInBlk >= mip0DepthInBlk);
xMajor = xMajor && (mip0WidthInBlk >= mip0DepthInBlk);
}
AddrMajorMode majorMode;
if (xMajor)
{
majorMode = ADDR_MAJOR_X;
}
else if (yMajor)
{
majorMode = ADDR_MAJOR_Y;
}
else
{
majorMode = ADDR_MAJOR_Z;
}
return majorMode;
}
static Dim3d GetDccCompressBlk(
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode,
UINT_32 bpp)
{
UINT_32 index = Log2(bpp >> 3);
Dim3d compressBlkDim;
if (IsThin(resourceType, swizzleMode))
{
compressBlkDim.w = CompressBlock2d[index].w;
compressBlkDim.h = CompressBlock2d[index].h;
compressBlkDim.d = 1;
}
else if (IsStandardSwizzle(resourceType, swizzleMode))
{
compressBlkDim = CompressBlock3dS[index];
}
else
{
compressBlkDim = CompressBlock3dZ[index];
}
return compressBlkDim;
}
Dim3d GetMipStartPos(
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode,
UINT_32 width,
UINT_32 height,
UINT_32 depth,
UINT_32 blockWidth,
UINT_32 blockHeight,
UINT_32 blockDepth,
UINT_32 mipId,
UINT_32* pMipTailOffset) const;
Dim3d GetMipTailDim(
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode,
@ -637,13 +643,13 @@ protected:
UINT_32 blockHeight,
UINT_32 blockDepth) const;
static BOOL_32 IsInMipTail(
BOOL_32 IsInMipTail(
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode,
Dim3d mipTailDim,
UINT_32 width,
UINT_32 height,
UINT_32 depth)
UINT_32 depth) const
{
BOOL_32 inTail = ((width <= mipTailDim.w) &&
(height <= mipTailDim.h) &&
@ -742,32 +748,15 @@ protected:
UINT_32 GetPipeXorBits(UINT_32 macroBlockBits) const;
UINT_32 GetBankXorBits(UINT_32 macroBlockBits) const;
virtual BOOL_32 HwlIsValidDisplaySwizzleMode(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const
{
ADDR_NOT_IMPLEMENTED();
return FALSE;
}
BOOL_32 IsValidDisplaySwizzleMode(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const
{
return HwlIsValidDisplaySwizzleMode(pIn);
}
virtual BOOL_32 HwlIsDce12() const
{
ADDR_NOT_IMPLEMENTED();
return FALSE;
}
BOOL_32 IsDce12() const { return HwlIsDce12(); }
ADDR_E_RETURNCODE ApplyCustomizedPitchHeight(
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
UINT_32 elementBytes,
UINT_32 widthAlignInElement,
UINT_32 pitchAlignInElement,
UINT_32* pPitch,
UINT_32* pHeight) const;
VOID ComputeQbStereoInfo(ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
UINT_32 m_se; ///< Number of shader engine
UINT_32 m_rbPerSe; ///< Number of render backend per shader engine
UINT_32 m_maxCompFrag; ///< Number of max compressed fragment
@ -782,6 +771,8 @@ protected:
UINT_32 m_blockVarSizeLog2; ///< Log2 of block var size
SwizzleModeFlags m_swizzleModeTable[ADDR_SW_MAX_TYPE]; ///< Swizzle mode table
private:
// Disallow the copy constructor
Lib(const Lib& a);

2416
src/amd/addrlib/gfx9/gfx9addrlib.cpp
View file

File diff suppressed because it is too large Load diff

188
src/amd/addrlib/gfx9/gfx9addrlib.h
View file

@ -25,10 +25,10 @@
*/
/**
****************************************************************************************************
************************************************************************************************************************
* @file gfx9addrlib.h
* @brief Contgfx9ns the Gfx9Lib class definition.
****************************************************************************************************
************************************************************************************************************************
*/
#ifndef __GFX9_ADDR_LIB_H__
@ -43,9 +43,9 @@ namespace V2
{
/**
****************************************************************************************************
************************************************************************************************************************
* @brief GFX9 specific settings structure.
****************************************************************************************************
************************************************************************************************************************
*/
struct Gfx9ChipSettings
{
@ -62,14 +62,15 @@ struct Gfx9ChipSettings
// Misc configuration bits
UINT_32 metaBaseAlignFix : 1;
UINT_32 reserved2 : 31;
UINT_32 depthPipeXorDisable : 1;
UINT_32 reserved2 : 30;
};
};
/**
****************************************************************************************************
************************************************************************************************************************
* @brief GFX9 data surface type.
****************************************************************************************************
************************************************************************************************************************
*/
enum Gfx9DataType
{
@ -79,10 +80,10 @@ enum Gfx9DataType
};
/**
****************************************************************************************************
************************************************************************************************************************
* @brief This class is the GFX9 specific address library
* function set.
****************************************************************************************************
************************************************************************************************************************
*/
class Gfx9Lib : public Lib
{
@ -98,6 +99,39 @@ protected:
Gfx9Lib(const Client* pClient);
virtual ~Gfx9Lib();
virtual BOOL_32 HwlIsStandardSwizzle(
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode) const
{
return m_swizzleModeTable[swizzleMode].isStd ||
(IsTex3d(resourceType) && m_swizzleModeTable[swizzleMode].isDisp);
}
virtual BOOL_32 HwlIsDisplaySwizzle(
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode) const
{
return IsTex2d(resourceType) && m_swizzleModeTable[swizzleMode].isDisp;
}
virtual BOOL_32 HwlIsThin(
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode) const
{
return ((IsTex2d(resourceType) == TRUE) ||
((IsTex3d(resourceType) == TRUE) &&
(m_swizzleModeTable[swizzleMode].isZ == FALSE) &&
(m_swizzleModeTable[swizzleMode].isStd == FALSE)));
}
virtual BOOL_32 HwlIsThick(
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode) const
{
return (IsTex3d(resourceType) &&
(m_swizzleModeTable[swizzleMode].isZ || m_swizzleModeTable[swizzleMode].isStd));
}
virtual ADDR_E_RETURNCODE HwlComputeHtileInfo(
const ADDR2_COMPUTE_HTILE_INFO_INPUT* pIn,
ADDR2_COMPUTE_HTILE_INFO_OUTPUT* pOut) const;
@ -122,6 +156,10 @@ protected:
const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn,
ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut) const;
virtual ADDR_E_RETURNCODE HwlComputeDccAddrFromCoord(
const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn,
ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut) const;
virtual UINT_32 HwlGetEquationIndex(
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
@ -183,13 +221,139 @@ protected:
return baseAlign;
}
virtual BOOL_32 HwlIsValidDisplaySwizzleMode(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const;
virtual ADDR_E_RETURNCODE HwlComputePipeBankXor(
const ADDR2_COMPUTE_PIPEBANKXOR_INPUT* pIn,
ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT* pOut) const;
virtual BOOL_32 HwlIsDce12() const { return m_settings.isDce12; }
virtual ADDR_E_RETURNCODE HwlComputeSlicePipeBankXor(
const ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT* pIn,
ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT* pOut) const;
virtual ADDR_E_RETURNCODE HwlComputeSubResourceOffsetForSwizzlePattern(
const ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT* pIn,
ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT* pOut) const;
virtual ADDR_E_RETURNCODE HwlGetPreferredSurfaceSetting(
const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn,
ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT* pOut) const;
virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoSanityCheck(
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const;
virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoTiled(
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
virtual ADDR_E_RETURNCODE HwlComputeSurfaceAddrFromCoordTiled(
const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const;
// Initialize equation table
VOID InitEquationTable();
ADDR_E_RETURNCODE ComputeStereoInfo(
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut,
UINT_32* pHeightAlign) const;
UINT_32 GetMipChainInfo(
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode,
UINT_32 bpp,
UINT_32 mip0Width,
UINT_32 mip0Height,
UINT_32 mip0Depth,
UINT_32 blockWidth,
UINT_32 blockHeight,
UINT_32 blockDepth,
UINT_32 numMipLevel,
ADDR2_MIP_INFO* pMipInfo) const;
VOID GetMetaMiptailInfo(
ADDR2_META_MIP_INFO* pInfo,
Dim3d mipCoord,
UINT_32 numMipInTail,
Dim3d* pMetaBlkDim) const;
Dim3d GetMipStartPos(
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode,
UINT_32 width,
UINT_32 height,
UINT_32 depth,
UINT_32 blockWidth,
UINT_32 blockHeight,
UINT_32 blockDepth,
UINT_32 mipId,
UINT_32 log2ElementBytes,
UINT_32* pMipTailBytesOffset) const;
AddrMajorMode GetMajorMode(
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode,
UINT_32 mip0WidthInBlk,
UINT_32 mip0HeightInBlk,
UINT_32 mip0DepthInBlk) const
{
BOOL_32 yMajor = (mip0WidthInBlk < mip0HeightInBlk);
BOOL_32 xMajor = (yMajor == FALSE);
if (IsThick(resourceType, swizzleMode))
{
yMajor = yMajor && (mip0HeightInBlk >= mip0DepthInBlk);
xMajor = xMajor && (mip0WidthInBlk >= mip0DepthInBlk);
}
AddrMajorMode majorMode;
if (xMajor)
{
majorMode = ADDR_MAJOR_X;
}
else if (yMajor)
{
majorMode = ADDR_MAJOR_Y;
}
else
{
majorMode = ADDR_MAJOR_Z;
}
return majorMode;
}
Dim3d GetDccCompressBlk(
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode,
UINT_32 bpp) const
{
UINT_32 index = Log2(bpp >> 3);
Dim3d compressBlkDim;
if (IsThin(resourceType, swizzleMode))
{
compressBlkDim.w = Block256_2d[index].w;
compressBlkDim.h = Block256_2d[index].h;
compressBlkDim.d = 1;
}
else if (IsStandardSwizzle(resourceType, swizzleMode))
{
compressBlkDim = Block256_3dS[index];
}
else
{
compressBlkDim = Block256_3dZ[index];
}
return compressBlkDim;
}
static const Dim3d Block256_3dS[MaxNumOfBpp];
static const Dim3d Block256_3dZ[MaxNumOfBpp];
static const UINT_32 MipTailOffset256B[];
static const SwizzleModeFlags SwizzleModeTable[ADDR_SW_MAX_TYPE];
// Max number of swizzle mode supported for equation
static const UINT_32 MaxSwMode = 32;
// Max number of resource type (2D/3D) supported for equation
@ -239,6 +403,8 @@ private:
UINT_32 mip0Width, UINT_32 mip0Height, UINT_32 mip0Depth,
UINT_32* pNumMetaBlkX, UINT_32* pNumMetaBlkY, UINT_32* pNumMetaBlkZ) const;
BOOL_32 IsValidDisplaySwizzleMode(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const;
Gfx9ChipSettings m_settings;
};

110
src/amd/addrlib/r800/ciaddrlib.cpp
View file

@ -711,6 +711,15 @@ ADDR_E_RETURNCODE CiLib::HwlComputeSurfaceInfo(
ADDR_E_RETURNCODE retCode = SiLib::HwlComputeSurfaceInfo(pIn, pOut);
if ((pIn->mipLevel > 0) &&
(pOut->tcCompatible == TRUE) &&
(pOut->tileMode != pIn->tileMode) &&
(m_settings.isVolcanicIslands == TRUE))
{
CheckTcCompatibility(pOut->pTileInfo, pIn->bpp, pOut->tileMode, pOut->tileType, pOut);
}
if (pOut->macroModeIndex == TileIndexNoMacroIndex)
{
pOut->macroModeIndex = TileIndexInvalid;
@ -1057,29 +1066,29 @@ VOID CiLib::HwlOverrideTileMode(
switch (tileMode)
{
case ADDR_TM_1D_TILED_THICK:
tileMode = ADDR_TM_1D_TILED_THIN1;
tileMode = ADDR_TM_1D_TILED_THIN1;
break;
case ADDR_TM_2D_TILED_XTHICK:
case ADDR_TM_2D_TILED_THICK:
tileMode = ADDR_TM_2D_TILED_THIN1;
tileMode = ADDR_TM_2D_TILED_THIN1;
break;
case ADDR_TM_3D_TILED_XTHICK:
case ADDR_TM_3D_TILED_THICK:
tileMode = ADDR_TM_3D_TILED_THIN1;
tileMode = ADDR_TM_3D_TILED_THIN1;
break;
case ADDR_TM_PRT_TILED_THICK:
tileMode = ADDR_TM_PRT_TILED_THIN1;
tileMode = ADDR_TM_PRT_TILED_THIN1;
break;
case ADDR_TM_PRT_2D_TILED_THICK:
tileMode = ADDR_TM_PRT_2D_TILED_THIN1;
tileMode = ADDR_TM_PRT_2D_TILED_THIN1;
break;
case ADDR_TM_PRT_3D_TILED_THICK:
tileMode = ADDR_TM_PRT_3D_TILED_THIN1;
tileMode = ADDR_TM_PRT_3D_TILED_THIN1;
break;
default:
@ -1563,39 +1572,7 @@ VOID CiLib::HwlSetupTileInfo(
if (flags.tcCompatible)
{
if (IsMacroTiled(tileMode))
{
if (inTileType != ADDR_DEPTH_SAMPLE_ORDER)
{
// Turn off tcCompatible for color surface if tileSplit happens. Depth/stencil
// tileSplit case was handled at tileIndex selecting time.
INT_32 tileIndex = pOut->tileIndex;
if ((tileIndex == TileIndexInvalid) && (IsTileInfoAllZero(pTileInfo) == FALSE))
{
tileIndex = HwlPostCheckTileIndex(pTileInfo, tileMode, inTileType, tileIndex);
}
if (tileIndex != TileIndexInvalid)
{
ADDR_ASSERT(static_cast<UINT_32>(tileIndex) < TileTableSize);
// Non-depth entries store a split factor
UINT_32 sampleSplit = m_tileTable[tileIndex].info.tileSplitBytes;
UINT_32 tileBytes1x = BITS_TO_BYTES(bpp * MicroTilePixels * thickness);
UINT_32 colorTileSplit = Max(256u, sampleSplit * tileBytes1x);
if (m_rowSize < colorTileSplit)
{
flags.tcCompatible = FALSE;
}
}
}
}
else
{
// Client should not enable tc compatible for linear and 1D tile modes.
flags.tcCompatible = FALSE;
}
CheckTcCompatibility(pTileInfo, bpp, tileMode, inTileType, pOut);
}
pOut->tcCompatible = flags.tcCompatible;
@ -2289,5 +2266,60 @@ BOOL_32 CiLib::DepthStencilTileCfgMatch(
return depthStencil2DTileConfigMatch;
}
/**
****************************************************************************************************
* CiLib::DepthStencilTileCfgMatch
*
* @brief
* Turn off TcCompatible if requirement is not met
* @return
* N/A
****************************************************************************************************
*/
VOID CiLib::CheckTcCompatibility(
const ADDR_TILEINFO* pTileInfo, ///< [in] input tile info
UINT_32 bpp, ///< [in] Bits per pixel
AddrTileMode tileMode, ///< [in] input tile mode
AddrTileType tileType, ///< [in] input tile type
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut ///< [out] out structure
) const
{
if (IsMacroTiled(tileMode))
{
if (tileType != ADDR_DEPTH_SAMPLE_ORDER)
{
// Turn off tcCompatible for color surface if tileSplit happens. Depth/stencil
// tileSplit case was handled at tileIndex selecting time.
INT_32 tileIndex = pOut->tileIndex;
if ((tileIndex == TileIndexInvalid) && (IsTileInfoAllZero(pTileInfo) == FALSE))
{
tileIndex = HwlPostCheckTileIndex(pTileInfo, tileMode, tileType, tileIndex);
}
if (tileIndex != TileIndexInvalid)
{
UINT_32 thickness = Thickness(tileMode);
ADDR_ASSERT(static_cast<UINT_32>(tileIndex) < TileTableSize);
// Non-depth entries store a split factor
UINT_32 sampleSplit = m_tileTable[tileIndex].info.tileSplitBytes;
UINT_32 tileBytes1x = BITS_TO_BYTES(bpp * MicroTilePixels * thickness);
UINT_32 colorTileSplit = Max(256u, sampleSplit * tileBytes1x);
if (m_rowSize < colorTileSplit)
{
pOut->tcCompatible = FALSE;
}
}
}
}
else
{
// Client should not enable tc compatible for linear and 1D tile modes.
pOut->tcCompatible = FALSE;
}
}
} // V1
} // Addr

4
src/amd/addrlib/r800/ciaddrlib.h
View file

@ -208,6 +208,10 @@ private:
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
VOID CheckTcCompatibility(
const ADDR_TILEINFO* pTileInfo, UINT_32 bpp, AddrTileMode tileMode,
AddrTileType tileType, ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
static const UINT_32 MacroTileTableSize = 16;
static const UINT_32 PrtMacroModeOffset = MacroTileTableSize / 2;
static const INT_32 MinDepth2DThinIndex = 0;

2
src/amd/addrlib/r800/egbaddrlib.cpp
View file

@ -4125,7 +4125,7 @@ UINT_32 EgBasedLib::ComputeFmaskResolvedBppFromNumSamples(
****************************************************************************************************
*/
BOOL_32 EgBasedLib::IsTileInfoAllZero(
ADDR_TILEINFO* pTileInfo)
const ADDR_TILEINFO* pTileInfo)
{
BOOL_32 allZero = TRUE;

2
src/amd/addrlib/r800/egbaddrlib.h
View file

@ -297,7 +297,7 @@ protected:
ADDR_TILEINFO* pTileInfo, ADDR_EQUATION* pEquation) const;
// Static functions
static BOOL_32 IsTileInfoAllZero(ADDR_TILEINFO* pTileInfo);
static BOOL_32 IsTileInfoAllZero(const ADDR_TILEINFO* pTileInfo);
static UINT_32 ComputeFmaskNumPlanesFromNumSamples(UINT_32 numSamples);
static UINT_32 ComputeFmaskResolvedBppFromNumSamples(UINT_32 numSamples);

26
src/amd/addrlib/r800/siaddrlib.cpp
View file

@ -2662,9 +2662,15 @@ ADDR_E_RETURNCODE SiLib::HwlComputeSurfaceInfo(
{
static const UINT_32 SiUncompressDepthTileIndex = 3;
if ((pIn->flags.prt == FALSE) &&
(m_uncompressDepthEqIndex != 0) &&
(tileIndex == SiUncompressDepthTileIndex))
if ((pIn->numSlices > 1) &&
(IsMacroTiled(pOut->tileMode) == TRUE) &&
(m_chipFamily == ADDR_CHIP_FAMILY_SI))
{
pOut->equationIndex = ADDR_INVALID_EQUATION_INDEX;
}
else if ((pIn->flags.prt == FALSE) &&
(m_uncompressDepthEqIndex != 0) &&
(tileIndex == SiUncompressDepthTileIndex))
{
pOut->equationIndex = m_uncompressDepthEqIndex + Log2(pIn->bpp >> 3);
}
@ -3344,19 +3350,19 @@ VOID SiLib::HwlOverrideTileMode(
switch (tileMode)
{
case ADDR_TM_PRT_TILED_THIN1:
tileMode = ADDR_TM_2D_TILED_THIN1;
tileMode = ADDR_TM_2D_TILED_THIN1;
break;
case ADDR_TM_PRT_TILED_THICK:
tileMode = ADDR_TM_2D_TILED_THICK;
tileMode = ADDR_TM_2D_TILED_THICK;
break;
case ADDR_TM_PRT_2D_TILED_THICK:
tileMode = ADDR_TM_2D_TILED_THICK;
tileMode = ADDR_TM_2D_TILED_THICK;
break;
case ADDR_TM_PRT_3D_TILED_THICK:
tileMode = ADDR_TM_3D_TILED_THICK;
tileMode = ADDR_TM_3D_TILED_THICK;
break;
default:
@ -3365,9 +3371,9 @@ VOID SiLib::HwlOverrideTileMode(
if (tileMode != pInOut->tileMode)
{
pInOut->tileMode = tileMode;
ADDR_ASSERT(pInOut->flags.prt == TRUE);
pInOut->tileMode = tileMode;
// Only PRT tile modes are overridden for now. Revisit this once new modes are added above.
pInOut->flags.prt = TRUE;
}
}