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Author	SHA1	Message	Date
Samuel Pitoiset	aea04d11b7	amd: allow addrlib to enable SIMD if possible ... The SIMD variants are way faster, the order of magnitude seems x10. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40996>	2026-04-21 10:14:42 +00:00
Caius-Moldovan-img	daeb52d38d	pco: Replace nir_shader_lower_instructions with nir_shader_*_pass ... Signed-off-by: Caius Moldovan <caius.moldovan@imgtec.com> Reviewed-by: Simon Perretta <simon.perretta@imgtec.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40390>	2026-04-21 09:17:28 +00:00
David Rosca	27dbe82800	ac/parse_ib: Fix printing enc recon VAs on VCN5 ... Fixes: f8f80c3700 ("ac/parse_ib: Fix VCN address parsing") Reviewed-by: Benjamin Cheng <benjamin.cheng@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41025>	2026-04-21 08:09:09 +00:00
Samuel Pitoiset	1fc8683281	radv: allow depth+stencil formats with host image copy ... Not super useful but it's supported. The NAVI10 crashes are expected and they are due to a bug in addrlib. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41000>	2026-04-21 08:57:31 +02:00
Samuel Pitoiset	4de652c78b	radv: add depth+stencil formats support with host image copy ... Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41000>	2026-04-21 08:57:31 +02:00
Samuel Pitoiset	fd95195f45	ac/surface: add stencil-only support for host mem->surf copies ... It's needed to tweak the surface info and to adjust the base pointer. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41000>	2026-04-21 08:57:31 +02:00
Brandon Jones	d1dd65d425	nir/opt_algebraic: fix fabs optimization ... This fixes a regression found in blender's unit testing, which called fabs(-0.0) and invoked an NIR optimization that is was not valid for the parameter -0.0. IEEE 754 requires that abs clear the sign bit for the value -0.0. Reviewed-by: Georg Lehmann <dadschoorse@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41060>	2026-04-21 04:10:29 +00:00
jinmiliu	e5392e3d5f	mesa/st: Set protected content context flag based on pipe context attributes ... If the PIPE_CONTEXT_PROTECTED flag is set in the context attributes, propagate this by enabling GL_CONTEXT_FLAG_PROTECTED_CONTENT_BIT_EXT on the corresponding Mesa GL context. Signed-off-by: jinmiliu <jinming.liu@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40998>	2026-04-21 03:14:35 +00:00
Sagar Ghuge	7a627fa8f3	anv: Fix Wa_14021821874, Wa_14018813551, Wa_14026600921 ... StackSizePerRay is the RTDispatchGlobals::AsyncStackSize and DisableRTGlobalsKnownValues is to interpret how many Max BVH levels we need to use. It's not relevant to Vulkan, since we have just 2 fixed BVH levels. Fixes: cb423ee6 ("anv: Fix Wa_14021821874, Wa_14018813551, Wa_14026600921") Fixes: c1a44e8d ("anv: force StackIDControl value for Wa_14021821874") Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41012>	2026-04-21 01:38:34 +00:00
Alyssa Rosenzweig	6397ddd15d	gallium: Drop post-processing filters ... Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Reviewed-by: Marek Olšák <maraeo@gmail.com> Reviewed-by: Emma Anholt <emma@anholt.net> Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com> Reviewed-by: Christian Gmeiner <cgmeiner@igalia.co Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5448>	2026-04-20 22:58:39 +00:00
Alyssa Rosenzweig	168141fbac	gallium: Drop users of post-processing filters ... Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Reviewed-by: Marek Olšák <maraeo@gmail.com> Reviewed-by: Emma Anholt <emma@anholt.net> Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com> Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5448>	2026-04-20 22:58:39 +00:00
Alyssa Rosenzweig	fd46a48ccc	jay/ra: only use stride=4 temps ... SIMD16: Totals from 56 (2.12% of 2647) affected shaders: Instrs: 541831 -> 542004 (+0.03%); split: -0.40%, +0.44% CodeSize: 8597680 -> 8597248 (-0.01%); split: -0.45%, +0.44% SIMD32: Totals: Instrs: 4858179 -> 4734713 (-2.54%); split: -2.78%, +0.24% CodeSize: 78651424 -> 76667440 (-2.52%); split: -2.76%, +0.24% Totals from 1108 (41.86% of 2647) affected shaders: Instrs: 4241312 -> 4117846 (-2.91%); split: -3.18%, +0.27% CodeSize: 68753152 -> 66769168 (-2.89%); split: -3.16%, +0.27% Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41064>	2026-04-20 22:32:12 +00:00
Alyssa Rosenzweig	1f62da938b	jay/ra: drop memory copy reordering ... No shader-db changes, and no longer required for correctness. Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41064>	2026-04-20 22:32:12 +00:00
Alyssa Rosenzweig	45845ea7f2	jay/ra: use accumulator for stride=4 swaps ... SIMD16: Totals: Instrs: 2767930 -> 2767190 (-0.03%) CodeSize: 44327408 -> 44312304 (-0.03%); split: -0.04%, +0.00% Totals from 142 (5.36% of 2647) affected shaders: Instrs: 658928 -> 658188 (-0.11%) CodeSize: 10514512 -> 10499408 (-0.14%); split: -0.16%, +0.01% SIMD32: Totals: Instrs: 4884039 -> 4858179 (-0.53%) CodeSize: 79079008 -> 78651424 (-0.54%); split: -0.54%, +0.00% Totals from 761 (28.75% of 2647) affected shaders: Instrs: 3803274 -> 3777414 (-0.68%) CodeSize: 61707728 -> 61280144 (-0.69%); split: -0.70%, +0.00% Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41064>	2026-04-20 22:32:12 +00:00
Alyssa Rosenzweig	489f883277	jay/ra: use accumulator for memory swaps ... SIMD1: Totals from 34 (1.28% of 2647) affected shaders: Instrs: 427731 -> 434349 (+1.55%); split: -0.03%, +1.58% CodeSize: 6773248 -> 6881136 (+1.59%); split: -0.04%, +1.63% Number of spill instructions: 1833 -> 1700 (-7.26%) Number of fill instructions: 2095 -> 1944 (-7.21%) SIMD32: Totals from 621 (23.46% of 2647) affected shaders: Instrs: 3663406 -> 3739089 (+2.07%); split: -0.62%, +2.68% CodeSize: 59392464 -> 60624704 (+2.07%); split: -0.61%, +2.68% Number of spill instructions: 52115 -> 50109 (-3.85%); split: -3.90%, +0.05% Number of fill instructions: 53864 -> 51355 (-4.66%) Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41064>	2026-04-20 22:32:11 +00:00
Alyssa Rosenzweig	2e5fd6da42	jay/ra: use accumulator for memory copies ... SIMD16: Totals from 34 (1.28% of 2647) affected shaders: Instrs: 424527 -> 427731 (+0.75%); split: -0.03%, +0.78% CodeSize: 6720896 -> 6773248 (+0.78%); split: -0.04%, +0.82% Number of spill instructions: 1967 -> 1833 (-6.81%) Number of fill instructions: 2247 -> 2095 (-6.76%) SIMD32: Totals: Instrs: 4691989 -> 4808356 (+2.48%); split: -0.46%, +2.94% CodeSize: 76011248 -> 77884320 (+2.46%); split: -0.46%, +2.92% Number of spill instructions: 54223 -> 52115 (-3.89%); split: -4.08%, +0.19% Number of fill instructions: 56519 -> 53864 (-4.70%) Totals from 606 (22.89% of 2647) affected shaders: Instrs: 3509511 -> 3625878 (+3.32%); split: -0.61%, +3.93% CodeSize: 56909488 -> 58782560 (+3.29%); split: -0.61%, +3.90% Number of spill instructions: 54223 -> 52115 (-3.89%); split: -4.08%, +0.19% Number of fill instructions: 56519 -> 53864 (-4.70%) Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41064>	2026-04-20 22:32:11 +00:00
Alyssa Rosenzweig	7d2a88a9e5	jay/ra: don't reserve registers when not spilling ... No changes at SIMD16. At SIMD32: Totals: Instrs: 4691895 -> 4691989 (+0.00%); split: -0.03%, +0.03% CodeSize: 76010880 -> 76011248 (+0.00%); split: -0.03%, +0.03% Number of spill instructions: 54369 -> 54223 (-0.27%) Number of fill instructions: 56668 -> 56519 (-0.26%) Totals from 71 (2.68% of 2647) affected shaders: Instrs: 75963 -> 76057 (+0.12%); split: -1.67%, +1.79% CodeSize: 1229792 -> 1230160 (+0.03%); split: -1.71%, +1.74% Number of spill instructions: 146 -> 0 (-inf%) Number of fill instructions: 149 -> 0 (-inf%) Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41064>	2026-04-20 22:32:11 +00:00
Alyssa Rosenzweig	e5bf153d4f	jay/lower_post_ra: drop old 2<-->8 lowering ... this XOR based lowering is no longer needed. Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41064>	2026-04-20 22:32:10 +00:00
Alyssa Rosenzweig	915af8e121	jay/lower_post_ra: remove SWAP macro ... Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41064>	2026-04-20 22:32:10 +00:00
Alyssa Rosenzweig	4c5ad7a832	jay/register_allocate: start using accumulators ... this lets us lower away 8<-->2 copies/swaps in a faster, more straightforward way by (ab)using accumulators. I think as an edge case this plays nicely enough with my plans to profit from accs for normal fma-heavy code. SIMD16: Totals: Instrs: 2761525 -> 2758108 (-0.12%) CodeSize: 44222384 -> 44167168 (-0.12%) Totals from 33 (1.25% of 2647) affected shaders: Instrs: 422130 -> 418713 (-0.81%) CodeSize: 6713680 -> 6658464 (-0.82%) SIMD32: Totals: Instrs: 4911601 -> 4691895 (-4.47%) CodeSize: 79553984 -> 76010880 (-4.45%) Totals from 947 (35.78% of 2647) affected shaders: Instrs: 4143501 -> 3923795 (-5.30%) CodeSize: 67174592 -> 63631488 (-5.27%) Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41064>	2026-04-20 22:32:10 +00:00
Alyssa Rosenzweig	53c1c076a8	jay: validate non-SSA accumulators ... just enough for us to do parallel copy lowering with them. Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41064>	2026-04-20 22:32:09 +00:00
Alyssa Rosenzweig	28cf0f52c1	jay/to_binary: handle packing accumulators ... Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41064>	2026-04-20 22:32:09 +00:00
Alyssa Rosenzweig	aa37d8b248	jay/print: deal with bare r0 copies ... Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41064>	2026-04-20 22:32:09 +00:00
Kenneth Graunke	e55af8793f	jay: Add missing ROR case ... Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41064>	2026-04-20 22:32:09 +00:00
Alyssa Rosenzweig	6c862b1951	jay: fix SEL types ... SEL.f32 flushes denorms but SEL.u32 does not. That means changing the type of the SEL is only justified if we know we're used as a float. This fixes miscompilation in cases like: ieq(1, bcsel(a, fneg(b), c)) Previously we'd be too greedy and form (a) SEL.f32 t, -b, c cmp.u32 t, 1 But that would inadvertently flush c which is an integer here. So just set the type based on what we're used as. Some regressions due to is_only_used_as_float not seeing through phis (..could probably be fixed?). Totals: Instrs: 2760796 -> 2761525 (+0.03%); split: -0.06%, +0.08% CodeSize: 44244128 -> 44222384 (-0.05%); split: -0.13%, +0.08% Totals from 945 (35.70% of 2647) affected shaders: Instrs: 1968645 -> 1969374 (+0.04%); split: -0.08%, +0.11% CodeSize: 31721968 -> 31700224 (-0.07%); split: -0.17%, +0.11% Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41064>	2026-04-20 22:32:09 +00:00
Alyssa Rosenzweig	b5898a418b	jay: relax mov type check ... prevents regression with next patch which turns u32 into s32. Totals: Instrs: 2764288 -> 2760796 (-0.13%) CodeSize: 44299920 -> 44244128 (-0.13%); split: -0.13%, +0.00% Totals from 193 (7.29% of 2647) affected shaders: Instrs: 255455 -> 251963 (-1.37%) CodeSize: 4160400 -> 4104608 (-1.34%); split: -1.34%, +0.00% Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41064>	2026-04-20 22:32:07 +00:00
Alyssa Rosenzweig	1b648326ac	jay: refuse to propagate ADDRESS copies ... at least until we have address RA.. Totals: Instrs: 2764282 -> 2764288 (+0.00%) CodeSize: 44299872 -> 44299920 (+0.00%) Totals from 2 (0.08% of 2647) affected shaders: Instrs: 4215 -> 4221 (+0.14%) CodeSize: 67456 -> 67504 (+0.07%) Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41064>	2026-04-20 22:32:07 +00:00
Alyssa Rosenzweig	56ffad0c3a	jay: call DCE an extra time ... Totals: Instrs: 2767235 -> 2765908 (-0.05%); split: -0.10%, +0.05% CodeSize: 44349488 -> 44328688 (-0.05%); split: -0.10%, +0.06% Totals from 347 (13.11% of 2647) affected shaders: Instrs: 718067 -> 716740 (-0.18%); split: -0.39%, +0.20% CodeSize: 11626032 -> 11605232 (-0.18%); split: -0.39%, +0.21% Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41064>	2026-04-20 22:32:06 +00:00
Alyssa Rosenzweig	d85eb51e17	jay/register_allocate: don't depend on indexing ... this can get messed up by optimizations. Totals: Instrs: 2768612 -> 2764317 (-0.16%); split: -0.29%, +0.13% CodeSize: 44367648 -> 44300352 (-0.15%); split: -0.28%, +0.13% Totals from 867 (32.75% of 2647) affected shaders: Instrs: 1694745 -> 1690450 (-0.25%); split: -0.47%, +0.22% CodeSize: 27387648 -> 27320352 (-0.25%); split: -0.46%, +0.21% Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41064>	2026-04-20 22:32:06 +00:00
Alyssa Rosenzweig	a964f321a5	jay: don't print internal without the flag ... Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41064>	2026-04-20 22:32:06 +00:00
Alyssa Rosenzweig	3a73c76373	jay: fix spiller coupling code ... Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41064>	2026-04-20 22:32:05 +00:00
Alyssa Rosenzweig	cd6c5a2f90	jay: improve spiller debug ... Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41064>	2026-04-20 22:32:05 +00:00
Alyssa Rosenzweig	d637554418	jay: fix simd32 deswizzle ... Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41064>	2026-04-20 22:32:05 +00:00
Alyssa Rosenzweig	f728e3cb05	jay: test logic op fusing ... Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41064>	2026-04-20 22:32:04 +00:00
Alyssa Rosenzweig	698223ccd1	jay/test-optimizer: fuse before/after cases ... new macro to DRY. Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41064>	2026-04-20 22:32:04 +00:00
Alyssa Rosenzweig	99796bff04	jay: fold logic ops ... Totals: Instrs: 2798036 -> 2784419 (-0.49%); split: -0.58%, +0.10% CodeSize: 44815024 -> 44614000 (-0.45%); split: -0.56%, +0.11% Number of fill instructions: 2270 -> 2280 (+0.44%) Totals from 1298 (49.04% of 2647) affected shaders: Instrs: 2165338 -> 2151721 (-0.63%); split: -0.75%, +0.13% CodeSize: 34865440 -> 34664416 (-0.58%); split: -0.72%, +0.15% Number of fill instructions: 1571 -> 1581 (+0.64%) Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41064>	2026-04-20 22:32:04 +00:00
Alyssa Rosenzweig	5d22e9d2a5	jay: allow predication of pure-flag instrs ... i.e. compares Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41064>	2026-04-20 22:32:03 +00:00
Alyssa Rosenzweig	2ab8a614dd	jay/register_allocate: tie predicated-defaults ... (if we can) Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41064>	2026-04-20 22:32:03 +00:00
Alyssa Rosenzweig	d74ada78c0	jay/assign_flags: handle predicated CMP ... the optimizer will generate this soon, so make sure flag RA can deal. Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41064>	2026-04-20 22:32:02 +00:00
Alyssa Rosenzweig	375945ea0b	jay/lower_pre_ra: skip predication ... otherwise the assert blows up Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41064>	2026-04-20 22:32:02 +00:00
Alyssa Rosenzweig	176b9a0f0c	jay/opt_dead_code: handle predication ... otherwise we'll get validation splat soon. Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41064>	2026-04-20 22:32:02 +00:00
Alyssa Rosenzweig	f63ab3eea5	jay/register_allocate: use standard builder name ... Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41064>	2026-04-20 22:32:02 +00:00
Alyssa Rosenzweig	f98e2b24bc	jay: fix the source pinning code ... I was just trying to get rid of the loop but it also generates better code. Totals: Instrs: 2806469 -> 2798036 (-0.30%); split: -0.33%, +0.02% CodeSize: 44950448 -> 44815024 (-0.30%); split: -0.32%, +0.02% Totals from 143 (5.40% of 2647) affected shaders: Instrs: 665554 -> 657121 (-1.27%); split: -1.37%, +0.10% CodeSize: 10611344 -> 10475920 (-1.28%); split: -1.37%, +0.10% Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41064>	2026-04-20 22:32:02 +00:00
Alyssa Rosenzweig	ad731766d3	jay: fix SEL implied pipe ... Pretty obscure, but this is not valid: < (1&W) sync.nop _.0 | $2.dst < (32&f2.0) sel.f32 g48, g48, -g40 | I@7 --- > (32&f2.0) sel.f32 g48, g48, -g40 | @7 $2.dst Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41064>	2026-04-20 22:32:01 +00:00
Alyssa Rosenzweig	9b423bfe94	jay: reduce calloc to malloc when memsetting after ... Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41064>	2026-04-20 22:32:01 +00:00
Alyssa Rosenzweig	b46d677aab	jay: reduce zeroing ... this is fully initialized when constructing phi webs anyway. Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41064>	2026-04-20 22:32:01 +00:00
Alyssa Rosenzweig	e20f8ab2b2	jay: generalize last kill code ... Totals: Instrs: 2815692 -> 2806469 (-0.33%); split: -0.44%, +0.11% CodeSize: 45100624 -> 44950448 (-0.33%); split: -0.44%, +0.11% Totals from 1292 (48.81% of 2647) affected shaders: Instrs: 2427684 -> 2418461 (-0.38%); split: -0.51%, +0.13% CodeSize: 38993984 -> 38843808 (-0.39%); split: -0.51%, +0.13% Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41064>	2026-04-20 22:32:00 +00:00
Alyssa Rosenzweig	70bfa005a5	jay: drop dead code ... Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41064>	2026-04-20 22:32:00 +00:00
Alyssa Rosenzweig	f39f6ce7ba	jay: strengthen assert ... Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41064>	2026-04-20 22:31:59 +00:00
Lionel Landwerlin	3388123f02	anv/apply_layout: move some helpers around ... No functional changes. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41047>	2026-04-20 21:53:35 +03:00