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radv: allow depth+stencil formats with host image copy
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Not super useful but it's supported. The NAVI10 crashes are expected
and they are due to a bug in addrlib.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41000>
This commit is contained in:
Samuel Pitoiset 2026-04-16 16:18:20 +02:00
parent 4de652c78b
commit 1fc8683281
2 changed files with 11 additions and 3 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

10
src/amd/ci/radv-navi10-fails.txt
View file

@ -71,6 +71,8 @@ dEQP-VK.api.copy_and_blit.core.use_after_copy.d32_sfloat_s8_uint.transfer_dst_op
# RADV_EXPERIMENTAL=hic regressions since addrlib for GFX11.7.
# Commenting the assertion in src/amd/addrlib/src/core/addrswizzler.cpp:117
# about power-of-two height block size fixes the issue.
dEQP-VK.image.host_image_copy.depth_stencil.d16_unorm_s8_uint,Crash
dEQP-VK.image.host_image_copy.depth_stencil.d32_sfloat_s8_uint,Crash
dEQP-VK.image.host_image_copy.depth_stencil.s8_uint,Crash
dEQP-VK.image.host_image_copy.large_images.image_to_memory_r8_unorm_4096_4096,Crash
dEQP-VK.image.host_image_copy.large_images.image_to_memory_r8_unorm_512_512,Crash
@ -80,6 +82,14 @@ dEQP-VK.image.host_image_copy.simple.a8_unorm.optimal.general_general.1_1,Crash
dEQP-VK.image.host_image_copy.simple.a8_unorm.optimal.general_general.1_4,Crash
dEQP-VK.image.host_image_copy.simple.a8_unorm.optimal.transfer_src_transfer_dst.1_1,Crash
dEQP-VK.image.host_image_copy.simple.a8_unorm.optimal.transfer_src_transfer_dst.1_4,Crash
dEQP-VK.image.host_image_copy.simple.d16_unorm_s8_uint.optimal.general_general.1_1,Crash
dEQP-VK.image.host_image_copy.simple.d16_unorm_s8_uint.optimal.general_general.1_4,Crash
dEQP-VK.image.host_image_copy.simple.d16_unorm_s8_uint.optimal.transfer_src_transfer_dst.1_1,Crash
dEQP-VK.image.host_image_copy.simple.d16_unorm_s8_uint.optimal.transfer_src_transfer_dst.1_4,Crash
dEQP-VK.image.host_image_copy.simple.d32_sfloat_s8_uint.optimal.general_general.1_1,Crash
dEQP-VK.image.host_image_copy.simple.d32_sfloat_s8_uint.optimal.general_general.1_4,Crash
dEQP-VK.image.host_image_copy.simple.d32_sfloat_s8_uint.optimal.transfer_src_transfer_dst.1_1,Crash
dEQP-VK.image.host_image_copy.simple.d32_sfloat_s8_uint.optimal.transfer_src_transfer_dst.1_4,Crash
dEQP-VK.image.host_image_copy.simple.r8_sint.optimal.general_general.1_1,Crash
dEQP-VK.image.host_image_copy.simple.r8_sint.optimal.general_general.1_4,Crash
dEQP-VK.image.host_image_copy.simple.r8_sint.optimal.transfer_src_transfer_dst.1_1,Crash

4
src/amd/vulkan/radv_formats.c
View file

@ -513,9 +513,7 @@ radv_physical_device_get_format_properties(struct radv_physical_device *pdev, Vk
buffer = 0;
}
/* No depth and stencil support yet. */
if (radv_host_image_copy_enabled(pdev) &&
(format != VK_FORMAT_D32_SFLOAT_S8_UINT && format != VK_FORMAT_D16_UNORM_S8_UINT)) {
if (radv_host_image_copy_enabled(pdev)) {
if (linear & VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_BIT)
linear |= VK_FORMAT_FEATURE_2_HOST_IMAGE_TRANSFER_BIT_EXT;