Commit graph

71908 commits

Author SHA1 Message Date
Francisco Jerez
ac7664e493 i965/gen7-8: Poke the 3DSTATE UAV access enable bits.
v2: Set the PS UAV-only bit on HSW (Ken).

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-08-11 15:07:39 +03:00
Francisco Jerez
acb6d90dc8 i965/gen7: Enable fragment shader dispatch if the program has image uniforms.
Shaders with image uniforms may have side effects.  Make sure that
fragment shader threads are dispatched if the shader has any image
uniforms.

v2: Use brw_stage_prog_data::nr_image_params to find out if the shader
    has image uniforms instead of checking core mesa data structures
    (Ken).

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-08-11 15:07:38 +03:00
Francisco Jerez
47f9b07e4c i965: Hook up image state upload.
v2: Add CS support.  Move the image_params array back to
    brw_stage_prog_data.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
2015-08-11 15:07:38 +03:00
Francisco Jerez
868f1ba0a4 i965: Reserve enough parameter entries for all image uniforms used in the program.
v2: Add CS support.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2015-08-11 15:07:38 +03:00
Francisco Jerez
87a3e02d9b i965: Define and initialize image parameter structure.
This will be used to pass image meta-data to the shader when we cannot
use typed surface reads and writes.  All entries except surface_idx
and size are otherwise unused and will get eliminated by the uniform
packing pass.  size will be used for bounds checking with some image
formats and will be useful for ARB_shader_image_size too.  surface_idx
is always used.

v2: Add CS support.  Move the image_params array back to
    brw_stage_prog_data.
v3: Improve documentation.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2015-08-11 15:07:38 +03:00
Francisco Jerez
3144844f5c i965: Implement surface state set-up for shader images.
v2: Add SKL support.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2015-08-11 15:07:38 +03:00
Francisco Jerez
2cdb24a7c2 i965: Fix brw_memory_barrier() for SKL.
This works as-is on SKL, only the assertion needs to be relaxed.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2015-08-11 15:07:38 +03:00
Francisco Jerez
f909469137 i965: Add SKL support to brw_miptree_get_horizontal_slice_pitch().
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2015-08-11 15:07:38 +03:00
Timothy Arceri
fe55ab2d12 glsl: Add missing spec quote about atomic counter in structs
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
2015-08-11 21:07:31 +10:00
Alex Deucher
87cea61b9e radeonsi: add new OLAND pci id
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: mesa-stable@lists.freedesktop.org
2015-08-10 22:44:55 -04:00
Ilia Mirkin
3fa1ca34cc nouveau: no need to do tnl wakeup, state updates are always hooked up
A TNL state update now requires a DrawBuffer to be set, which it isn't
early on in context creation. Since we init swtnl from context init,
this caused crashes.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91570
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.6" <mesa-stable@lists.freedesktop.org>
2015-08-10 17:43:44 -04:00
Jason Ekstrand
8a688bee83 i965/fs: Make resolve_source_modifiers consistent with the vec4 version
Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-08-10 12:04:06 -07:00
Jason Ekstrand
7068a6409c i965/vec4_visitor: Make some function arguments const references
Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-08-10 12:04:06 -07:00
Jason Ekstrand
1bb339493c i965/fs: Don't do redundant RA setup on IVB+
Acked-by: Matt Turner <mattst88@gmail.com>
2015-08-10 12:04:04 -07:00
Jason Ekstrand
0ac65abb46 i965/fs: Use dispatch_width instead of reg_width in alloc_reg_sets
reg_width is kind of an outdated concept.

Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-08-10 11:59:04 -07:00
Jason Ekstrand
bdcc8f3230 ra: Delete the conflict lists in ra_set_finalize
They are never used after the set is finalized so there's no reason to keep
them around.

Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-08-10 11:58:58 -07:00
Jason Ekstrand
7539ac7fe2 ra: Refactor ra_set_finalize
All this commit does is change an early return to an if with an else
clause.

Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-08-10 11:58:45 -07:00
Jason Ekstrand
c1d9b3ae0b i965/vec4_nir: Properly handle integer multiplies on BDW+
Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-08-10 11:45:43 -07:00
Jason Ekstrand
1d658cf879 i965/vec4_nir: Do boolean source modifier resolves on BDW+
On BDW+, the negation source modifier on NOT, AND, OR, and XOR, is actually
a boolean negate and not an integer negate.  However, NIR's soruce
modifiers are the integer version.  We have to resolve it with a MOV prior
to emitting the actual instruction.  This is basically the same thing we do
in the FS backend.

Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-08-10 11:45:43 -07:00
Jason Ekstrand
5e1c1c2fcb i965/vec4-nir: Handle boolean resolvese on ILK-
The analysis code was already there and running, we just weren't doing
anything with the result of it yet.

Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-08-10 11:45:43 -07:00
Jason Ekstrand
1d4e698466 i965/nir: Don't mark bany or ball instructions for resolve
Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-08-10 11:45:43 -07:00
Jason Ekstrand
17c9781661 i965/nir: Use nir_op_info.output_type for determining when to resolve
Previously, we were explicitly listing every instruction that needs a
resolve.  However, those instructions were precicely the ones that returned
booleans so there's no reason why we shouldn't just have that check.  Also,
all of the reduction opcodes such as bany and ball were missing so it
didn't properly flag stuff on vec4.  If an opcode gets added in the future
that returns a bool but doesn't need a resolve, we can special-case that.

Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-08-10 11:45:43 -07:00
Jason Ekstrand
9901aeb1c7 mesa/format_utils: Add src_bits == dst_bits cases to unorm_to_unorm
This better ensures that the src_bits == dst_bits case gets optimized away.

Reviewed-by: Neil Roberts <neil@linux.intel.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2015-08-10 11:11:47 -07:00
Marek Olšák
7e5d56394b gallium/radeon: add a debug flag not to use write combining (v2)
v2: just clear the flag before the allocation

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-08-10 18:26:44 +02:00
Rob Clark
7bfe8cf4a4 freedreno/a4xx: add s8/z32/z32_s8x24 support
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2015-08-10 07:12:54 -04:00
Rob Clark
fcb8a04c9d freedreno: update generated headers
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2015-08-10 07:12:54 -04:00
Rob Clark
2d6a889e8b freedreno/a4xx: fix vpsrepl for blit shaders
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2015-08-10 07:12:54 -04:00
Rob Clark
d2f669e6c7 freedreno/a4xx: clear cached fp when switching blit prog
For gmem restore (mem2gmem), we swap blit programs, in order to have a
different frag shader for depth vs color restore.  But we weren't
actually clearing the cached fp, so it would not actually change the
frag shader as expected.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2015-08-10 07:12:54 -04:00
Rob Clark
6dabf45597 freedreno/a3xx: clear cached fp when switching blit prog
For gmem restore (mem2gmem), we swap blit programs, in order to have a
different frag shader for depth vs color restore.  But we weren't
actually clearing the cached fp, so it would not actually change the
frag shader as expected.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2015-08-10 07:12:54 -04:00
Marta Lofstedt
08f2dfe343 mesa/es3.1: Allow Multisampled FrameBufferTextures
GLES 3.1 must be allowed to use multisampled framebuffer textures.

Signed-off-by: Marta Lofstedt <marta.lofstedt@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2015-08-10 13:49:41 +03:00
Marta Lofstedt
b6d014f0ba mesa/es3.1: Pass sample count check for multisampled textures
v3 : Removed space in comment.

Signed-off-by: Marta Lofstedt <marta.lofstedt@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2015-08-10 13:34:49 +03:00
Oded Gabbay
2ac171a7db mesa: clear existing swizzle info before bitwise-OR
This patch fixes a bug in big-endian treatment, where the previous
swizzle info wasn't cleared before a new swizzle info was inserted into
the format field using a bitwise-OR operation.

v2: use MESA_ARRAY_FORMAT_SWIZZLE_*_MASK instead of numeric constants
v3: align according to coding style

Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
CC: "10.5 10.6" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2015-08-09 23:59:23 -07:00
Jose Fonseca
1eaa29cb30 util: Use LONG_MAX instead of LONG_BIT.
More portable.  Based on Roland Scheidegger's idea.

Tested with roundevent_test on Linux, MinGW, and MSVC.

https://bugs.freedesktop.org/show_bug.cgi?id=91591

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-08-10 00:08:55 +01:00
Jose Fonseca
497a22a727 scons: Build roundevent_test.
Reviewed-by: Roland Scheidegger <sroland@vmware.co>
2015-08-10 00:07:27 +01:00
Jose Fonseca
21ccdbdb5d util: Cope with LONG_BIT not being defined on Windows.
Neither MSVC nor MinGW defines LONG_BIT.  For MSVC this was not a problem as
it doesn't define __x86_64__ macro (it's GCC specific.)

However on Windows long type is guaranteed to be 32bits.

Also add an #error, as GCC will just warn, not throw any error, when no
value is returned.

Trivial.
2015-08-09 11:32:43 +01:00
Jose Fonseca
eb643db30e gallium: GCC 4.9 allows to include tmmintrin.h without -msse3.
Fixes build with MinGW x86_64 build with GCC 4.9, due to conflicting
definition _mm_shuffle_epi8 of u_sse.h and system headers.

Trivial.
2015-08-09 11:32:43 +01:00
Jose Fonseca
512aa0647f util: Rename PURE to ATTRIBUTE_PURE.
To avoid collission with windows.h's PURE macro.

We could consider eventually renaming to __pure, but that would require
further care, so it's left to the future.

Reviewed-by: Brian Paul <brianp@vmware.com>
2015-08-09 11:32:43 +01:00
Boyan Ding
27141f984d egl/x11: Fix driver_name acquisition
We don't need to free driverName string from dri2 reply, on the other
hand, the driver name acquired from loader doesn't need duplication.

Fixes: 45e110bad9 (egl/x11: trust our loader over the xserver for the
drivername)

Reported-by: Timothy Arceri <t_arceri@yahoo.com.au>
Signed-off-by: Boyan Ding <boyan.j.ding@gmail.com>
[Emil Velikov: use brackets for both branches of conditional]
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2015-08-08 13:36:17 +01:00
Ben Widawsky
a1adf0b3fe i965/skl: (trivial) Remove invalid comment about thread counts
This should have been a part of:
commit 7eaacc1678
Author: Ben Widawsky <benjamin.widawsky@intel.com>
Date:   Wed Jul 29 12:35:24 2015 -0700

    i965/skl: Add production thread counts and URB size

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2015-08-07 13:48:27 -07:00
Chris Wilson
ffadfbf5d0 i965: Fix HW binding tables editing
Since the introduction of new gl_shader_stages in

commit a2af956963
Author: Fabian Bieler <fabianbieler@fastmail.fm>
Date:   Fri Mar 7 10:19:09 2014 +0100

    mesa: add tessellation shader enums

the translation table for the stage into the HW binding table edit
command was broken, and so we used illegal commands. Fix the array
initialisation to be impervious to changes in the gl_shader_stages enum
and add the asserts that would have caught the issue earlier.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Matt Turner <mattst88@gmail.com>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-08-07 20:57:05 +01:00
Alexander von Gluck IV
ba651967a2 egl/dri2: Fix include path of u_atomic.h introduced e7e29189
This was causing a failure to build on SCons due to a missing
-Isrc/egl. Instead of adding in that path, lets just -Isrc/
and include "utils/u_atomic.h".

Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-08-07 14:31:25 -05:00
Emil Velikov
6de9a03bed egl/x11: don't crash if dri2_dpy->conn is NULL
Identical to commit 60e9c35b3a0(egl/x11: bail out if we cannot fetch
the xcb connection) but for the swrast codepath.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2015-08-07 19:22:27 +01:00
Emil Velikov
2c7b6cf512 egl/x11: auth with xserver before attempting to open the dri module
No real change, apart from keeping the calls to the underlying winsys
(x11) next to each other. Just like platform_wayland.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2015-08-07 19:16:59 +01:00
Emil Velikov
45e110bad9 egl/x11: trust our loader over the xserver for the drivername
This is a port of commit 7bd95ec437a(dri2: Trust our own driver name
lookup over the server's.) from glx/dri2.

v2: Add newline between code and multiline comment. (Matt)

Cc: Julien Isorce <julien.isorce@gmail.com>
Reported-by: Julien Isorce <julien.isorce@gmail.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2015-08-07 19:16:10 +01:00
Emil Velikov
faf0f811e3 egl/x11: open the device from within dri2_x11_connect()
Allows us, with the next commit, to use alternative driver_name rather
than the one from xserver.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2015-08-07 19:15:02 +01:00
Emil Velikov
beddb0a237 egl/x11: fetch the device_name prior to driver_name
With the follow up commits we're about to further reshuffle things. Thus
we'll honour our our driver_name lookup (src/loader), and use the one
provided by xserver as a fall-back.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2015-08-07 19:14:37 +01:00
Emil Velikov
bf66988b08 egl/x11: remove dri2_dpy->conn checks
If the connection is NULL we won't be able to get here.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2015-08-07 19:14:20 +01:00
Emil Velikov
60e9c35b3a egl/x11: bail out if we cannot fetch the xcb connection
The documentation of xcb_connection_has_error() does not mention
what will happen, if NULL is fed to the function.

Upon closer look (props to Matt), it seems that we'll crash as the
implementation dereferences conn.

This will also allow us to remove the dri2_dpy->conn checking with the
next commit.

v2: Reword commit message as per Matt's findings.

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2015-08-07 19:13:35 +01:00
Emil Velikov
75ce7919d6 vc4: add missing nir include, to fix the build
Cc: 10.6 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2015-08-07 18:38:10 +01:00
Emil Velikov
4fa0cd17b7 vc4: automake: remove unused include
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2015-08-07 18:37:43 +01:00