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i965/fs: Don't do redundant RA setup on IVB+

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Acked-by: Matt Turner <mattst88@gmail.com>
This commit is contained in:
Jason Ekstrand 2015-07-31 08:36:35 -07:00
parent 0ac65abb46
commit 1bb339493c
1 changed files with 9 additions and 0 deletions
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9
src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
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@ -79,6 +79,15 @@ brw_alloc_reg_set(struct brw_compiler *compiler, int dispatch_width)
int base_reg_count = BRW_MAX_GRF;
int index = (dispatch_width / 8) - 1;
if (dispatch_width > 8 && devinfo->gen >= 7) {
/* For IVB+, we don't need the PLN hacks or the even-reg alignment in
* SIMD16. Therefore, we can use the exact same register sets for
* SIMD16 as we do for SIMD8 and we don't need to recalculate them.
*/
compiler->fs_reg_sets[index] = compiler->fs_reg_sets[0];
return;
}
/* The registers used to make up almost all values handled in the compiler
* are a scalar value occupying a single register (or 2 registers in the
* case of SIMD16, which is handled by dividing base_reg_count by 2 and