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https://gitlab.freedesktop.org/mesa/mesa.git
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freedreno: update generated headers
Signed-off-by: Rob Clark <robclark@freedesktop.org>
This commit is contained in:
Rob Clark
parent
2d6a889e8b
commit
fcb8a04c9d
5 changed files with 183 additions and 5 deletions
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@ -14,7 +14,7 @@ The rules-ng-ng source files this header was generated from are:
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2015-05-20 20:03:14)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14968 bytes, from 2015-05-20 20:12:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 66709 bytes, from 2015-05-20 20:03:14)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 60800 bytes, from 2015-07-10 14:00:13)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 63728 bytes, from 2015-08-05 18:07:28)
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Copyright (C) 2013-2015 by the following authors:
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- Rob Clark <robdclark@gmail.com> (robclark)
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@ -14,7 +14,7 @@ The rules-ng-ng source files this header was generated from are:
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2015-05-20 20:03:14)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14968 bytes, from 2015-05-20 20:12:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 66709 bytes, from 2015-05-20 20:03:14)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 60800 bytes, from 2015-07-10 14:00:13)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 63728 bytes, from 2015-08-05 18:07:28)
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Copyright (C) 2013-2015 by the following authors:
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- Rob Clark <robdclark@gmail.com> (robclark)
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@ -14,7 +14,7 @@ The rules-ng-ng source files this header was generated from are:
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2015-05-20 20:03:14)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14968 bytes, from 2015-05-20 20:12:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 66709 bytes, from 2015-05-20 20:03:14)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 60800 bytes, from 2015-07-10 14:00:13)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 63728 bytes, from 2015-08-05 18:07:28)
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Copyright (C) 2013-2015 by the following authors:
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- Rob Clark <robdclark@gmail.com> (robclark)
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@ -227,6 +227,7 @@ enum a4xx_depth_format {
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DEPTH4_NONE = 0,
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DEPTH4_16 = 1,
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DEPTH4_24_8 = 2,
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DEPTH4_32 = 3,
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};
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enum a4xx_tess_spacing {
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@ -820,6 +821,23 @@ static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op v
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#define REG_A4XX_RB_STENCIL_CONTROL2 0x00002107
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#define A4XX_RB_STENCIL_CONTROL2_STENCIL_BUFFER 0x00000001
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#define REG_A4XX_RB_STENCIL_INFO 0x00002108
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#define A4XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001
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#define A4XX_RB_STENCIL_INFO_STENCIL_BASE__MASK 0xfffff000
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#define A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT 12
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static inline uint32_t A4XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val)
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{
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return ((val >> 12) << A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT) & A4XX_RB_STENCIL_INFO_STENCIL_BASE__MASK;
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}
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#define REG_A4XX_RB_STENCIL_PITCH 0x00002109
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#define A4XX_RB_STENCIL_PITCH__MASK 0xffffffff
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#define A4XX_RB_STENCIL_PITCH__SHIFT 0
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static inline uint32_t A4XX_RB_STENCIL_PITCH(uint32_t val)
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{
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return ((val >> 5) << A4XX_RB_STENCIL_PITCH__SHIFT) & A4XX_RB_STENCIL_PITCH__MASK;
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}
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#define REG_A4XX_RB_STENCILREFMASK 0x0000210b
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#define A4XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff
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#define A4XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0
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@ -1479,6 +1497,76 @@ static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
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#define REG_A4XX_SP_HS_LENGTH_REG 0x00002312
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#define REG_A4XX_SP_DS_PARAM_REG 0x0000231a
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#define A4XX_SP_DS_PARAM_REG_POSREGID__MASK 0x000000ff
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#define A4XX_SP_DS_PARAM_REG_POSREGID__SHIFT 0
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static inline uint32_t A4XX_SP_DS_PARAM_REG_POSREGID(uint32_t val)
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{
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return ((val) << A4XX_SP_DS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_DS_PARAM_REG_POSREGID__MASK;
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}
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#define A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__MASK 0xfff00000
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#define A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__SHIFT 20
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static inline uint32_t A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR(uint32_t val)
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{
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return ((val) << A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__SHIFT) & A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__MASK;
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}
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static inline uint32_t REG_A4XX_SP_DS_OUT(uint32_t i0) { return 0x0000231b + 0x1*i0; }
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static inline uint32_t REG_A4XX_SP_DS_OUT_REG(uint32_t i0) { return 0x0000231b + 0x1*i0; }
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#define A4XX_SP_DS_OUT_REG_A_REGID__MASK 0x000001ff
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#define A4XX_SP_DS_OUT_REG_A_REGID__SHIFT 0
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static inline uint32_t A4XX_SP_DS_OUT_REG_A_REGID(uint32_t val)
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{
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return ((val) << A4XX_SP_DS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_DS_OUT_REG_A_REGID__MASK;
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}
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#define A4XX_SP_DS_OUT_REG_A_COMPMASK__MASK 0x00001e00
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#define A4XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT 9
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static inline uint32_t A4XX_SP_DS_OUT_REG_A_COMPMASK(uint32_t val)
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{
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return ((val) << A4XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_DS_OUT_REG_A_COMPMASK__MASK;
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}
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#define A4XX_SP_DS_OUT_REG_B_REGID__MASK 0x01ff0000
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#define A4XX_SP_DS_OUT_REG_B_REGID__SHIFT 16
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static inline uint32_t A4XX_SP_DS_OUT_REG_B_REGID(uint32_t val)
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{
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return ((val) << A4XX_SP_DS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_DS_OUT_REG_B_REGID__MASK;
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}
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#define A4XX_SP_DS_OUT_REG_B_COMPMASK__MASK 0x1e000000
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#define A4XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT 25
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static inline uint32_t A4XX_SP_DS_OUT_REG_B_COMPMASK(uint32_t val)
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{
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return ((val) << A4XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_DS_OUT_REG_B_COMPMASK__MASK;
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}
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static inline uint32_t REG_A4XX_SP_DS_VPC_DST(uint32_t i0) { return 0x0000232c + 0x1*i0; }
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static inline uint32_t REG_A4XX_SP_DS_VPC_DST_REG(uint32_t i0) { return 0x0000232c + 0x1*i0; }
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#define A4XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
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#define A4XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT 0
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static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC0(uint32_t val)
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{
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return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK;
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}
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#define A4XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
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#define A4XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT 8
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static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC1(uint32_t val)
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{
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return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK;
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}
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#define A4XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
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#define A4XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT 16
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static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC2(uint32_t val)
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{
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return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK;
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}
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#define A4XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
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#define A4XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT 24
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static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val)
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{
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return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK;
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}
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#define REG_A4XX_SP_DS_OBJ_OFFSET_REG 0x00002334
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#define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
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#define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
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@ -1501,6 +1589,82 @@ static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
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#define REG_A4XX_SP_DS_LENGTH_REG 0x00002339
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#define REG_A4XX_SP_GS_PARAM_REG 0x00002341
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#define A4XX_SP_GS_PARAM_REG_POSREGID__MASK 0x000000ff
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#define A4XX_SP_GS_PARAM_REG_POSREGID__SHIFT 0
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static inline uint32_t A4XX_SP_GS_PARAM_REG_POSREGID(uint32_t val)
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{
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return ((val) << A4XX_SP_GS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_GS_PARAM_REG_POSREGID__MASK;
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}
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#define A4XX_SP_GS_PARAM_REG_PRIMREGID__MASK 0x0000ff00
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#define A4XX_SP_GS_PARAM_REG_PRIMREGID__SHIFT 8
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static inline uint32_t A4XX_SP_GS_PARAM_REG_PRIMREGID(uint32_t val)
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{
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return ((val) << A4XX_SP_GS_PARAM_REG_PRIMREGID__SHIFT) & A4XX_SP_GS_PARAM_REG_PRIMREGID__MASK;
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}
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#define A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__MASK 0xfff00000
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#define A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__SHIFT 20
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static inline uint32_t A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR(uint32_t val)
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{
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return ((val) << A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__SHIFT) & A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__MASK;
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}
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static inline uint32_t REG_A4XX_SP_GS_OUT(uint32_t i0) { return 0x00002342 + 0x1*i0; }
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static inline uint32_t REG_A4XX_SP_GS_OUT_REG(uint32_t i0) { return 0x00002342 + 0x1*i0; }
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#define A4XX_SP_GS_OUT_REG_A_REGID__MASK 0x000001ff
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#define A4XX_SP_GS_OUT_REG_A_REGID__SHIFT 0
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static inline uint32_t A4XX_SP_GS_OUT_REG_A_REGID(uint32_t val)
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{
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return ((val) << A4XX_SP_GS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_GS_OUT_REG_A_REGID__MASK;
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}
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#define A4XX_SP_GS_OUT_REG_A_COMPMASK__MASK 0x00001e00
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#define A4XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT 9
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static inline uint32_t A4XX_SP_GS_OUT_REG_A_COMPMASK(uint32_t val)
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{
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return ((val) << A4XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_GS_OUT_REG_A_COMPMASK__MASK;
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}
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#define A4XX_SP_GS_OUT_REG_B_REGID__MASK 0x01ff0000
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#define A4XX_SP_GS_OUT_REG_B_REGID__SHIFT 16
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static inline uint32_t A4XX_SP_GS_OUT_REG_B_REGID(uint32_t val)
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{
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return ((val) << A4XX_SP_GS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_GS_OUT_REG_B_REGID__MASK;
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}
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#define A4XX_SP_GS_OUT_REG_B_COMPMASK__MASK 0x1e000000
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#define A4XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT 25
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static inline uint32_t A4XX_SP_GS_OUT_REG_B_COMPMASK(uint32_t val)
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{
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return ((val) << A4XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_GS_OUT_REG_B_COMPMASK__MASK;
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}
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static inline uint32_t REG_A4XX_SP_GS_VPC_DST(uint32_t i0) { return 0x00002353 + 0x1*i0; }
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static inline uint32_t REG_A4XX_SP_GS_VPC_DST_REG(uint32_t i0) { return 0x00002353 + 0x1*i0; }
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#define A4XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
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#define A4XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT 0
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static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC0(uint32_t val)
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{
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return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK;
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}
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#define A4XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
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#define A4XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT 8
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static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC1(uint32_t val)
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{
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return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK;
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}
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#define A4XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
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#define A4XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT 16
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static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC2(uint32_t val)
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{
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return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK;
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}
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#define A4XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
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#define A4XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT 24
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static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC3(uint32_t val)
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{
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return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK;
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}
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#define REG_A4XX_SP_GS_OBJ_OFFSET_REG 0x0000235b
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#define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
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#define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
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@ -1702,6 +1866,18 @@ static inline uint32_t A4XX_VFD_CONTROL_3_REGID_VTXCNT(uint32_t val)
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{
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return ((val) << A4XX_VFD_CONTROL_3_REGID_VTXCNT__SHIFT) & A4XX_VFD_CONTROL_3_REGID_VTXCNT__MASK;
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}
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#define A4XX_VFD_CONTROL_3_REGID_TESSX__MASK 0x00ff0000
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#define A4XX_VFD_CONTROL_3_REGID_TESSX__SHIFT 16
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static inline uint32_t A4XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val)
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{
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return ((val) << A4XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A4XX_VFD_CONTROL_3_REGID_TESSX__MASK;
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}
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#define A4XX_VFD_CONTROL_3_REGID_TESSY__MASK 0xff000000
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#define A4XX_VFD_CONTROL_3_REGID_TESSY__SHIFT 24
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static inline uint32_t A4XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val)
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{
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return ((val) << A4XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A4XX_VFD_CONTROL_3_REGID_TESSY__MASK;
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}
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#define REG_A4XX_VFD_CONTROL_4 0x00002204
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@ -2498,6 +2674,8 @@ static inline uint32_t A4XX_UNKNOWN_20F7(float val)
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#define REG_A4XX_UNKNOWN_22D7 0x000022d7
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#define REG_A4XX_UNKNOWN_2352 0x00002352
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#define REG_A4XX_TEX_SAMP_0 0x00000000
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#define A4XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001
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#define A4XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006
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@ -14,7 +14,7 @@ The rules-ng-ng source files this header was generated from are:
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2015-05-20 20:03:14)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14968 bytes, from 2015-05-20 20:12:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 66709 bytes, from 2015-05-20 20:03:14)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 60800 bytes, from 2015-07-10 14:00:13)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 63728 bytes, from 2015-08-05 18:07:28)
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Copyright (C) 2013-2015 by the following authors:
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- Rob Clark <robdclark@gmail.com> (robclark)
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@ -14,7 +14,7 @@ The rules-ng-ng source files this header was generated from are:
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2015-05-20 20:03:14)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14968 bytes, from 2015-05-20 20:12:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 66709 bytes, from 2015-05-20 20:03:14)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 60800 bytes, from 2015-07-10 14:00:13)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 63728 bytes, from 2015-08-05 18:07:28)
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Copyright (C) 2013-2015 by the following authors:
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- Rob Clark <robdclark@gmail.com> (robclark)
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|
|
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Loading…
Add table
Reference in a new issue