Instead of the state part of the simulator being baked in, it's now
broken out into a pluggable component that the simulator talks to via a
function pointer interface. This will let us run the simulator without
the full state simulator under the hood.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30703>
out_args->scratch_offset and in_wg_id_x will alias on <gfx9.
To avoid the conversion code reading a garbage WG ID, move the
scratch/ring offset writing to the very end.
Fixes: 1e354172 ("radv,aco: Convert 1D ray launches to 2D")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30707>
A loop that looks like:
loop {
do_work_1();
if (cond) {
break;
} else {
}
do_work_2();
break;
}
We can't pull that break ahead of do_work_1() after hoisting the initial
do_work_1() out of the loop. So bail in this case.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11711
Fixes: 6b4b044739 ("nir/opt_loop: add loop peeling optimization")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30702>
We should use `.zink-turnip-collabora-manual-rules` instead of
`.collabora-turnip-manual-rules`, since the former correctly reacts to
the zink+turnip file changes.
Fixes: 69eac6dd15 ("ci/a618: Add zink-tu-a618-full")
Reported-by: Valentine Burley <valentine.burley@gmail.com>
Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30698>
In pratical the only change here is that batch_bo_pool
are captured to error dumps.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30676>
Those are batch buffers that are not allocated from batch_bo_pool,
so they were left out of error capture without the capture-all
parameter.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30676>
Make sure to take new GRF size into consideration and adjust the
indirect offset according to new size so that when we do the indirect
load with address register, we load right values.
This helps pass the following tests:
- dEQP-VK.binding_model.descriptor_buffer.mutable_descriptor.*geom*
- dEQP-VK.ray_query.*geometry_shader.*
Backport-to: 24.2
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30679>
In !25925 I attempted to fix an error spam caused by the disk cache not
creating parent directories of the cache directory when needed,
resulting in failure to create the disk cache. Presumably that is bad
for performance.
Unfortunately I did a really bad job and only fixed the edge case where
the cache dir is given by $MESA_SHADER_CACHE_DIR rather than the general
case. Here I attempt to be more comprehensive.
Fixes#8294
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30160>
ir3_const_state is shared between the binning and non-binning variants.
The non-binning variant is compiled first and sets up ir3_const_state
after which the binning variant is not supposed to modify it anymore. If
it would, things may go haywire since the layout of the constant state
will change after the non-binning variant already finished compiling.
Currently, the ir3_const_state() accessor takes care of the sharing
(i.e., it returns the non-binning const state for the binning variant)
but nothing would be prevent the binning variant from accidentally
modifying the state. This is handled by restraint from its users.
This commit tries to make it more difficult to accidentally modify the
const state by the binning shader by making the following changes:
- ir3_const_state(): the same logic as before but now returns a const
pointer to prevent the binning variant from (accidentally) modifying
the const state.
- ir3_const_state_mut(): returns a non-const pointer but asserts that it
is not called by the binning variant.
As a corollary ir3_get_driver_ubo() also had to be split in two variants
(const and non-const) as it is called with a pointer to one of the
fields of ir3_const_state.
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30256>
ir3_cp uses the const state to lower immediates. It doesn't take the
binning variant into account so in theory, it could add immediates to
the const state for the binning variant, modifying the state after its
layout had already been established for the non-binning variant.
In practice, this probably works fine as the immediates are the last
section of the const state so the layout wouldn't be changed by ir3_cp.
However, there is very little benefit in doing this (the chances for an
immediate being necessary in the binning variant but not in the
non-binning variant are small) so it's better to stick to the global
invariant of not changing the const state in the binning variant.
This commit makes sure that immediates are never added by ir3_cp for the
binning variant. Some refactoring was necessary, however, since the
lookup and modification of the const state were a bit intertwined. More
specifically, currently, the immediate storage in the const state would
always be enlarged by ir3_cp whenever its full, even when it might
actually contain the immediate. To fix this, the logic is split in two
functions: ir3_const_find_imm() for lookup (allowed to be called by the
binning variant), and ir3_const_add_imm for adding immediates (not
allowed to be called by the binning variant).
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30256>
We used to remove the unused outputs for the binning pass in ir3. Even
though DCE would be able to clean up most of the mess, there could still
be some left: most notably, unused control flow would not be cleaned up
(leaving some weird branches to empty blocks). Instead of teaching ir3
how to clean this up, it makes more sense to do this at the NIR level,
where we can also benefit from other optimizations.
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30256>
Neither VK-GL-CTS nor dri2_setup_screen() require it, unlike
texture_2D_image and texture_cubemap_image. Crucially, older etnaviv
generations and vc4 in general do not support 3d textures.
Thus drop the requirement in order to support EGL 1.5 across the board.
Signed-off-by: Robert Mader <robert.mader@collabora.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30680>
Basically what 004e0eb3ab ("panfrost: use RGB1 component ordering
for R5G6B5 pixel formats") was doing in the gallium driver, but
applied to panvk this time.
Fixes: 004e0eb3ab ("panfrost: use RGB1 component ordering for R5G6B5 pixel formats")
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30685>
load_global_constant_uniform_block_intel is equivalent in terms of
loading, then for the predicate we just do a bcsel afterward in places
where that is required.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30659>
BLIT_EVENT_STORE_AND_CLEAR presumably swallows the BLIT_EVENT_CLEAR
at the start of the next bin. Should be faster than separate events.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30270>
CP_BLIT is used only for VK_FORMAT_E5B9G9R9_UFLOAT_PACK32 until we mark
it as renderable (on A7XX E5B9G9R9 is renderable format).
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30270>
Instead of reproting an VK_ERROR_INCOMPATIBLE_DRIVER we were crashing as
device->model was init after this error check.
Tested on G57 but should work the same on all unsupported arch.
Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Fixes: f7f9b3d170 ("panvk: Move to vk_properties")
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30686>
There is a hardcoded limit of 4 layers in all structs, so make sure
drivers will not return more.
Reviewed-By: Sil Vilerino <sivileri@microsoft.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30151>
This just adds support for allowing worst case image sizing with no
specified profiles and for using inline queries.
Reviewed-by: Lynne <dev@lynne.ee>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30671>
This handles the new inlines queries for VK_KHR_video_maintenance1
(Decode doesn't do queries on AMD at the moment).
Reviewed-by: Lynne <dev@lynne.ee>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30671>
The static assert used in encode deref modes used the fact there was
less than 16 modes that we wanted to compress as an opportunity to reuse
MODE_ENC_GENERIC_BIT as it just happened to represent 16. However if we
add more than 16 modes i.e need to compress to 6 bits not 5 bits then
MODE_ENC_GENERIC_BIT becomes 32 and the logic in the assert breaks.
Instead we more precisely make sure MODE_ENC_GENERIC_BIT is large
enough to fit all but the last 4 generic modes and that the last 4 modes
defined in the enum are in fact the 4 generic modes.
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30654>
