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freedreno: Define SP_DITHER_CNTL (0xA9AC)

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Seems to be the same as RB_DITHER_CNTL. Both get set to 0x5555
when dithering is enabled on the proprietary gles driver.

Signed-off-by: Karmjit Mahil <karmjit.mahil@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30536>
This commit is contained in:
Karmjit Mahil 2024-08-06 13:09:17 +02:00 • committed by Marge Bot
parent 9241af23e5
commit 110201cfd8
3 changed files with 12 additions and 7 deletions
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5
src/freedreno/common/freedreno_devices.py
View file

@ -934,7 +934,6 @@ a730_raw_magic_regs = [
[A6XXRegs.REG_A7XX_GRAS_UNKNOWN_80A7, 0x00000000],
[A6XXRegs.REG_A7XX_HLSQ_UNKNOWN_A9AC, 0x00000000],
[A6XXRegs.REG_A7XX_RB_UNKNOWN_8E79, 0x00000000],
[A6XXRegs.REG_A7XX_RB_UNKNOWN_8899, 0x00000000],
[A6XXRegs.REG_A7XX_RB_UNKNOWN_88F5, 0x00000000],
@ -1046,7 +1045,6 @@ add_gpus([
[A6XXRegs.REG_A7XX_GRAS_UNKNOWN_80A7, 0x00000000],
[A6XXRegs.REG_A7XX_HLSQ_UNKNOWN_A9AC, 0x00000000],
[A6XXRegs.REG_A7XX_RB_UNKNOWN_8E79, 0x00000000],
[A6XXRegs.REG_A7XX_RB_UNKNOWN_8899, 0x00000000],
[A6XXRegs.REG_A7XX_RB_UNKNOWN_88F5, 0x00000000],
@ -1135,7 +1133,6 @@ add_gpus([
[A6XXRegs.REG_A7XX_GRAS_UNKNOWN_80A7, 0x00000000],
[A6XXRegs.REG_A7XX_HLSQ_UNKNOWN_A9AC, 0x00000000],
[A6XXRegs.REG_A7XX_RB_UNKNOWN_8E79, 0x00000000],
[A6XXRegs.REG_A7XX_RB_UNKNOWN_8899, 0x00000000],
[A6XXRegs.REG_A7XX_RB_UNKNOWN_88F5, 0x00000000],
@ -1222,7 +1219,6 @@ add_gpus([
[A6XXRegs.REG_A7XX_GRAS_UNKNOWN_80A7, 0x00000000],
[A6XXRegs.REG_A7XX_HLSQ_UNKNOWN_A9AC, 0x00000000],
[A6XXRegs.REG_A7XX_RB_UNKNOWN_8E79, 0x00000000],
[A6XXRegs.REG_A7XX_RB_UNKNOWN_8899, 0x00000000],
[A6XXRegs.REG_A7XX_RB_UNKNOWN_88F5, 0x00000000],
@ -1297,7 +1293,6 @@ add_gpus([
[A6XXRegs.REG_A7XX_GRAS_UNKNOWN_80A7, 0x00000000],
[A6XXRegs.REG_A7XX_HLSQ_UNKNOWN_A9AC, 0x00000000],
[A6XXRegs.REG_A7XX_RB_UNKNOWN_8899, 0x00000000],
[A6XXRegs.REG_A7XX_RB_UNKNOWN_88F5, 0x00000000],
[A6XXRegs.REG_A7XX_RB_UNKNOWN_8C34, 0x00000000],

12
src/freedreno/registers/adreno/a6xx.xml
View file

@ -5448,8 +5448,16 @@ to upconvert to 32b float internally?
<bitfield name="CONSTS_LOAD_DISABLE" pos="0" type="boolean"/>
</reg32>
<!-- Always 0 -->
<reg32 offset="0xa9ac" name="HLSQ_UNKNOWN_A9AC" variants="A7XX-" usage="cmd"/>
<reg32 offset="0xa9ac" name="SP_DITHER_CNTL" variants="A7XX-" usage="cmd">
<bitfield name="DITHER_MODE_MRT0" low="0" high="1" type="adreno_rb_dither_mode"/>
<bitfield name="DITHER_MODE_MRT1" low="2" high="3" type="adreno_rb_dither_mode"/>
<bitfield name="DITHER_MODE_MRT2" low="4" high="5" type="adreno_rb_dither_mode"/>
<bitfield name="DITHER_MODE_MRT3" low="6" high="7" type="adreno_rb_dither_mode"/>
<bitfield name="DITHER_MODE_MRT4" low="8" high="9" type="adreno_rb_dither_mode"/>
<bitfield name="DITHER_MODE_MRT5" low="10" high="11" type="adreno_rb_dither_mode"/>
<bitfield name="DITHER_MODE_MRT6" low="12" high="13" type="adreno_rb_dither_mode"/>
<bitfield name="DITHER_MODE_MRT7" low="14" high="15" type="adreno_rb_dither_mode"/>
</reg32>
<!-- Used in VK_KHR_fragment_shading_rate -->
<reg32 offset="0xa9ad" name="HLSQ_UNKNOWN_A9AD" variants="A7XX-" usage="cmd"/>

2
src/freedreno/vulkan/tu_cmd_buffer.cc
View file

@ -1287,6 +1287,8 @@ tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
emit_rb_ccu_cntl<CHIP>(cs, cmd->device, false);
cmd->state.ccu_state = TU_CMD_CCU_SYSMEM;
tu_cs_emit_write_reg(cs, REG_A7XX_SP_DITHER_CNTL, 0);
for (size_t i = 0; i < ARRAY_SIZE(phys_dev->info->a6xx.magic_raw); i++) {
auto magic_reg = phys_dev->info->a6xx.magic_raw[i];
if (!magic_reg.reg)