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tu/a7xx: Use generic clear for image clears
CP_BLIT is used only for VK_FORMAT_E5B9G9R9_UFLOAT_PACK32 until we mark it as renderable (on A7XX E5B9G9R9 is renderable format). Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30270>
This commit is contained in:
Danylo Piliaiev
Marge Bot
parent
21511c02a3
commit
80a50269a2
2 changed files with 217 additions and 33 deletions
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@ -1870,47 +1870,80 @@ event_blit_setup(struct tu_cs *cs,
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.clear_mask = clear_mask, ));
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}
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struct event_blit_dst_view {
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const struct tu_image *image;
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const struct fdl6_view *view;
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uint32_t layer;
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uint64_t depth_addr;
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uint32_t depth_pitch;
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uint64_t stencil_addr;
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uint32_t stencil_pitch;
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};
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static event_blit_dst_view
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blt_view_from_tu_view(const struct tu_image_view *iview,
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uint32_t layer)
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{
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struct event_blit_dst_view blt_view;
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blt_view.image = iview->image;
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blt_view.view = &iview->view;
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blt_view.layer = layer;
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if (iview->image->vk.format == VK_FORMAT_D32_SFLOAT_S8_UINT) {
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blt_view.depth_addr =
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iview->depth_base_addr + iview->depth_layer_size * layer;
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blt_view.depth_pitch = iview->depth_pitch;
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blt_view.stencil_addr =
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iview->stencil_base_addr + iview->stencil_layer_size * layer;
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blt_view.stencil_pitch = iview->stencil_pitch;
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}
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return blt_view;
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}
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template <chip CHIP>
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static void
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event_blit_run(struct tu_cmd_buffer *cmd,
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struct tu_cs *cs,
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const struct tu_render_pass_attachment *att,
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const struct tu_image_view *iview,
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bool separate_stencil,
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uint32_t layer)
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const event_blit_dst_view *blt_view,
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bool separate_stencil)
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{
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tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_DST_INFO, 4);
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if (iview->image->vk.format == VK_FORMAT_D32_SFLOAT_S8_UINT) {
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if (blt_view->image->vk.format == VK_FORMAT_D32_SFLOAT_S8_UINT) {
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if (!separate_stencil) {
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tu_cs_emit(cs, tu_image_view_depth(iview, RB_BLIT_DST_INFO));
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tu_cs_emit_qw(
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cs, iview->depth_base_addr + iview->depth_layer_size * layer);
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tu_cs_emit(cs, A6XX_RB_2D_DST_PITCH(iview->depth_pitch).value);
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tu_cs_emit(cs, tu_fdl_view_depth(blt_view->view, RB_BLIT_DST_INFO));
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tu_cs_emit_qw(cs, blt_view->depth_addr);
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tu_cs_emit(cs, A6XX_RB_2D_DST_PITCH(blt_view->depth_pitch).value);
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tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_FLAG_DST, 3);
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tu_cs_image_flag_ref(cs, &iview->view, layer);
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tu_cs_image_flag_ref(cs, blt_view->view, blt_view->layer);
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} else {
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tu_cs_emit(cs, tu_image_view_stencil(iview, RB_BLIT_DST_INFO) &
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tu_cs_emit(cs, tu_fdl_view_stencil(blt_view->view, RB_BLIT_DST_INFO) &
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~A6XX_RB_BLIT_DST_INFO_FLAGS);
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tu_cs_emit_qw(
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cs, iview->stencil_base_addr + iview->stencil_layer_size * layer);
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tu_cs_emit(cs, A6XX_RB_BLIT_DST_PITCH(iview->stencil_pitch).value);
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tu_cs_emit_qw(cs, blt_view->stencil_addr);
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tu_cs_emit(cs, A6XX_RB_BLIT_DST_PITCH(blt_view->stencil_pitch).value);
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}
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} else {
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tu_cs_emit(cs, iview->view.RB_BLIT_DST_INFO);
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tu_cs_image_ref_2d<CHIP>(cs, &iview->view, layer, false);
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tu_cs_emit(cs, blt_view->view->RB_BLIT_DST_INFO);
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tu_cs_image_ref_2d<CHIP>(cs, blt_view->view, blt_view->layer, false);
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tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_FLAG_DST, 3);
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tu_cs_image_flag_ref(cs, &iview->view, layer);
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tu_cs_image_flag_ref(cs, blt_view->view, blt_view->layer);
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}
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if (att->format == VK_FORMAT_D32_SFLOAT_S8_UINT && separate_stencil) {
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tu_cs_emit_regs(cs,
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A6XX_RB_BLIT_BASE_GMEM(
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tu_attachment_gmem_offset_stencil(cmd, att, layer)));
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} else {
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tu_cs_emit_regs(cs, A6XX_RB_BLIT_BASE_GMEM(
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tu_attachment_gmem_offset(cmd, att, layer)));
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if (att) {
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if (att->format == VK_FORMAT_D32_SFLOAT_S8_UINT && separate_stencil) {
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tu_cs_emit_regs(
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cs, A6XX_RB_BLIT_BASE_GMEM(tu_attachment_gmem_offset_stencil(
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cmd, att, blt_view->layer)));
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} else {
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tu_cs_emit_regs(cs, A6XX_RB_BLIT_BASE_GMEM(tu_attachment_gmem_offset(
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cmd, att, blt_view->layer)));
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}
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}
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tu_emit_event_write<CHIP>(cmd, cs, FD_BLIT);
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@ -1936,8 +1969,10 @@ tu7_generic_layer_clear(struct tu_cmd_buffer *cmd,
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tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 4);
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tu_cs_emit_array(cs, clear_vals, 4);
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event_blit_dst_view blt_view = blt_view_from_tu_view(iview, layer);
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event_blit_setup(cs, att, BLIT_EVENT_CLEAR, clear_mask);
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event_blit_run<A7XX>(cmd, cs, att, iview, separate_stencil, layer);
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event_blit_run<A7XX>(cmd, cs, att, &blt_view, separate_stencil);
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}
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@ -3038,11 +3073,11 @@ TU_GENX(tu_resolve_sysmem);
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template <chip CHIP>
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static void
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clear_image(struct tu_cmd_buffer *cmd,
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struct tu_image *image,
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const VkClearValue *clear_value,
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const VkImageSubresourceRange *range,
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VkImageAspectFlags aspect_mask)
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clear_image_cp_blit(struct tu_cmd_buffer *cmd,
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struct tu_image *image,
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const VkClearValue *clear_value,
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const VkImageSubresourceRange *range,
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VkImageAspectFlags aspect_mask)
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{
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uint32_t level_count = vk_image_subresource_level_count(&image->vk, range);
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uint32_t layer_count = vk_image_subresource_layer_count(&image->vk, range);
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@ -3097,6 +3132,132 @@ clear_image(struct tu_cmd_buffer *cmd,
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ops->teardown(cmd, cs);
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}
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static void
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clear_image_event_blit(struct tu_cmd_buffer *cmd,
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struct tu_image *image,
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const VkClearValue *clear_value,
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const VkImageSubresourceRange *range,
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VkImageAspectFlags aspect_mask)
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{
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uint32_t level_count = vk_image_subresource_level_count(&image->vk, range);
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uint32_t layer_count = vk_image_subresource_layer_count(&image->vk, range);
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VkFormat vk_format = image->vk.format;
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if (vk_format == VK_FORMAT_D32_SFLOAT_S8_UINT) {
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if (aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT)
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vk_format = VK_FORMAT_S8_UINT;
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else
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vk_format = VK_FORMAT_D32_SFLOAT;
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}
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enum pipe_format format = vk_format_to_pipe_format(vk_format);
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if (image->layout[0].depth0 > 1) {
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assert(layer_count == 1);
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assert(range->baseArrayLayer == 0);
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}
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struct tu_cs *cs = &cmd->cs;
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tu_cs_emit_regs(cs,
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A7XX_RB_BLIT_CLEAR_MODE(.clear_mode = CLEAR_MODE_SYSMEM));
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tu_cs_emit_pkt4(cs, REG_A6XX_RB_UNKNOWN_88D0, 1);
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tu_cs_emit(cs, 0);
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tu_cs_emit_regs(
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cs, A6XX_RB_BLIT_INFO(
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.type = BLIT_EVENT_CLEAR,
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.sample_0 = vk_format_is_int(vk_format) ||
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vk_format_is_depth_or_stencil(vk_format),
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.depth = vk_format_is_depth_or_stencil(vk_format),
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.clear_mask = aspect_write_mask_generic_clear(format, aspect_mask)));
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uint32_t clear_vals[4] = {};
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pack_blit_event_clear_value(clear_value, format, clear_vals);
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tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 4);
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tu_cs_emit_array(cs, clear_vals, 4);
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for (unsigned level = 0; level < level_count; level++) {
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if (image->layout[0].depth0 > 1)
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layer_count =
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u_minify(image->layout[0].depth0, range->baseMipLevel + level);
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uint32_t width =
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u_minify(image->layout[0].width0, range->baseMipLevel + level);
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uint32_t height =
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u_minify(image->layout[0].height0, range->baseMipLevel + level);
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tu_cs_emit_regs(
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cs, A6XX_RB_BLIT_SCISSOR_TL(.x = 0, .y = 0),
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A6XX_RB_BLIT_SCISSOR_BR(.x = width - 1, .y = height - 1));
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struct fdl6_view dst;
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const VkImageSubresourceLayers subresource = {
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.aspectMask = aspect_mask,
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.mipLevel = range->baseMipLevel + level,
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.baseArrayLayer = range->baseArrayLayer,
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.layerCount = 1,
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};
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tu_image_view_copy_blit<A7XX>(&dst, image, format, &subresource, 0, false);
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for (uint32_t layer = 0; layer < layer_count; layer++) {
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struct event_blit_dst_view blt_view = {
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.image = image,
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.view = &dst,
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.layer = layer,
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};
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if (image->vk.format == VK_FORMAT_D32_SFLOAT_S8_UINT) {
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uint32_t real_level = range->baseMipLevel + level;
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uint32_t real_layer = range->baseArrayLayer + layer;
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if (aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT) {
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struct fdl_layout *layout = &image->layout[0];
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blt_view.depth_addr =
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image->iova +
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fdl_surface_offset(layout, real_level, real_layer);
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blt_view.depth_pitch = fdl_pitch(layout, real_level);
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} else {
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struct fdl_layout *layout = &image->layout[1];
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blt_view.stencil_addr =
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image->iova +
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fdl_surface_offset(layout, real_level, real_layer);
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blt_view.stencil_pitch = fdl_pitch(layout, real_level);
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}
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}
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event_blit_run<A7XX>(cmd, cs, NULL, &blt_view,
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aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT);
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}
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}
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}
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static bool
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use_generic_clear_for_image_clear(struct tu_cmd_buffer *cmd,
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struct tu_image *image)
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{
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return cmd->device->physical_device->info->a7xx.has_generic_clear &&
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/* A7XX supports R9G9B9E5_FLOAT as color attachment and supports
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* generic clears for it. A7XX TODO: allow R9G9B9E5_FLOAT
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* attachments.
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*/
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image->vk.format != VK_FORMAT_E5B9G9R9_UFLOAT_PACK32;
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}
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template <chip CHIP>
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static void
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clear_image(struct tu_cmd_buffer *cmd,
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struct tu_image *image,
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const VkClearValue *clear_value,
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const VkImageSubresourceRange *range,
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VkImageAspectFlags aspect_mask)
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{
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if (use_generic_clear_for_image_clear(cmd, image)) {
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clear_image_event_blit(cmd, image, clear_value, range, aspect_mask);
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} else {
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clear_image_cp_blit<CHIP>(cmd, image, clear_value, range, aspect_mask);
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}
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}
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template <chip CHIP>
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VKAPI_ATTR void VKAPI_CALL
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tu_CmdClearColorImage(VkCommandBuffer commandBuffer,
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@ -3109,8 +3270,16 @@ tu_CmdClearColorImage(VkCommandBuffer commandBuffer,
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VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
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VK_FROM_HANDLE(tu_image, image, image_h);
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for (unsigned i = 0; i < rangeCount; i++)
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if (use_generic_clear_for_image_clear(cmd, image)) {
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/* Generic clear doesn't go through CCU (or other caches). */
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cmd->state.cache.flush_bits |=
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TU_CMD_FLAG_CCU_INVALIDATE_COLOR | TU_CMD_FLAG_WAIT_FOR_IDLE;
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tu_emit_cache_flush<CHIP>(cmd);
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}
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for (unsigned i = 0; i < rangeCount; i++) {
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clear_image<CHIP>(cmd, image, (const VkClearValue*) pColor, pRanges + i, VK_IMAGE_ASPECT_COLOR_BIT);
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}
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}
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TU_GENX(tu_CmdClearColorImage);
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@ -3126,6 +3295,14 @@ tu_CmdClearDepthStencilImage(VkCommandBuffer commandBuffer,
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VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
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VK_FROM_HANDLE(tu_image, image, image_h);
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if (use_generic_clear_for_image_clear(cmd, image)) {
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/* Generic clear doesn't go through CCU (or other caches). */
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cmd->state.cache.flush_bits |= TU_CMD_FLAG_CCU_INVALIDATE_COLOR |
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TU_CMD_FLAG_CCU_INVALIDATE_DEPTH |
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TU_CMD_FLAG_WAIT_FOR_IDLE;
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tu_emit_cache_flush<CHIP>(cmd);
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}
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for (unsigned i = 0; i < rangeCount; i++) {
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const VkImageSubresourceRange *range = &pRanges[i];
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@ -3787,7 +3964,8 @@ tu_emit_blit(struct tu_cmd_buffer *cmd,
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event_blit_setup(cs, attachment, blit_event_type, 0x0);
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for_each_layer(i, attachment->clear_views, cmd->state.framebuffer->layers) {
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event_blit_run<CHIP>(cmd, cs, attachment, iview, separate_stencil, i);
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event_blit_dst_view blt_view = blt_view_from_tu_view(iview, i);
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event_blit_run<CHIP>(cmd, cs, attachment, &blt_view, separate_stencil);
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}
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tu_flush_for_access(&cmd->state.cache, TU_ACCESS_BLIT_WRITE_GMEM,
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@ -14,11 +14,17 @@
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#define TU_MAX_PLANE_COUNT 3
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#define tu_fdl_view_stencil(view, x) \
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(((view)->x & ~A6XX_##x##_COLOR_FORMAT__MASK) | A6XX_##x##_COLOR_FORMAT(FMT6_8_UINT))
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#define tu_fdl_view_depth(view, x) \
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(((view)->x & ~A6XX_##x##_COLOR_FORMAT__MASK) | A6XX_##x##_COLOR_FORMAT(FMT6_32_FLOAT))
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#define tu_image_view_stencil(iview, x) \
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((iview->view.x & ~A6XX_##x##_COLOR_FORMAT__MASK) | A6XX_##x##_COLOR_FORMAT(FMT6_8_UINT))
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tu_fdl_view_stencil(&iview->view, x)
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#define tu_image_view_depth(iview, x) \
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((iview->view.x & ~A6XX_##x##_COLOR_FORMAT__MASK) | A6XX_##x##_COLOR_FORMAT(FMT6_32_FLOAT))
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tu_fdl_view_depth(&iview->view, x)
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struct tu_image
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{
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