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intel/brw: Make 16-bit ishl, ishr, and ushr SSA friendly

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No shader-db changes on any Intel platform.

fossil-db:

All Intel platforms had similar results. (Meteor Lake shown)
Totals:
Instrs: 152536266 -> 152535897 (-0.00%); split: -0.00%, +0.00%
Cycle count: 17124901233 -> 17112329592 (-0.07%); split: -0.07%, +0.00%
Spill count: 78571 -> 78525 (-0.06%)
Fill count: 148178 -> 148132 (-0.03%)

Totals from 210 (0.03% of 633223) affected shaders:
Instrs: 514525 -> 514156 (-0.07%); split: -0.16%, +0.08%
Cycle count: 4003540698 -> 3990969057 (-0.31%); split: -0.32%, +0.00%
Spill count: 15632 -> 15586 (-0.29%)
Fill count: 26241 -> 26195 (-0.18%)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30650>
This commit is contained in:
Ian Romanick 2024-08-09 16:14:35 -07:00 • committed by Marge Bot
parent 2c47ad7774
commit e9c151fde6
1 changed files with 9 additions and 6 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

15
src/intel/compiler/brw_fs_nir.cpp
View file

@ -1633,8 +1633,9 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr,
*/
case nir_op_ishl:
if (instr->def.bit_size < 32) {
bld.AND(result, op[1], brw_imm_ud(instr->def.bit_size - 1));
bld.SHL(result, op[0], result);
bld.SHL(result,
op[0],
bld.AND(op[1], brw_imm_ud(instr->def.bit_size - 1)));
} else {
bld.SHL(result, op[0], op[1]);
}
@ -1642,8 +1643,9 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr,
break;
case nir_op_ishr:
if (instr->def.bit_size < 32) {
bld.AND(result, op[1], brw_imm_ud(instr->def.bit_size - 1));
bld.ASR(result, op[0], result);
bld.ASR(result,
op[0],
bld.AND(op[1], brw_imm_ud(instr->def.bit_size - 1)));
} else {
bld.ASR(result, op[0], op[1]);
}
@ -1651,8 +1653,9 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr,
break;
case nir_op_ushr:
if (instr->def.bit_size < 32) {
bld.AND(result, op[1], brw_imm_ud(instr->def.bit_size - 1));
bld.SHR(result, op[0], result);
bld.SHR(result,
op[0],
bld.AND(op[1], brw_imm_ud(instr->def.bit_size - 1)));
} else {
bld.SHR(result, op[0], op[1]);
}