mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
synced 2025-12-26 17:10:11 +01:00
nouveau/mme/tu104: Break the state simulator into a pluggable component
Instead of the state part of the simulator being baked in, it's now broken out into a pluggable component that the simulator talks to via a function pointer interface. This will let us run the simulator without the full state simulator under the hood. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30703>
This commit is contained in:
Faith Ekstrand
Marge Bot
parent
79e0b632a2
commit
aabd7941ce
3 changed files with 247 additions and 141 deletions
26
src/nouveau/mme/mme_sim.h
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26
src/nouveau/mme/mme_sim.h
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@ -0,0 +1,26 @@
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/*
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* Copyright © 2022 Collabora Ltd.
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* SPDX-License-Identifier: MIT
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*/
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#ifndef MME_SIM_H
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#define MME_SIM_H
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#include "nv_device_info.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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struct mme_sim_state_ops {
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uint32_t (*load)(void *handler);
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uint32_t (*state)(void *handler, uint16_t addr);
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void (*mthd)(void *handler, uint16_t addr, uint32_t data);
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void (*barrier)(void *handler);
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uint32_t *(*map_dram)(void *handler, uint32_t idx);
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};
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#ifdef __cplusplus
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}
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#endif
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#endif /* MME_SIM_H */
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@ -12,36 +12,11 @@
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#include "nv_push_clc597.h"
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struct mme_tu104_sim {
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uint32_t param_count;
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const uint32_t *params;
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const struct mme_sim_state_ops *state_ops;
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void *state_handler;
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uint32_t load[2];
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/* Bound memory ranges */
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uint32_t mem_count;
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struct mme_tu104_sim_mem *mems;
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/* SET_MME_MEM_ADDRESS_A/B */
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uint64_t mem_addr;
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/* RAM, accessed by DREAD/DWRITE */
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struct {
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uint32_t data[MME_TU104_DRAM_COUNT];
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/* SET_MME_MEM_RAM_ADDRESS */
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uint32_t addr;
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} ram;
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struct {
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struct {
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uint32_t data[1024];
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uint64_t count;
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} read_fifo;
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} dma;
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/* NVC597_SET_MME_SHADOW_SCRATCH(i) */
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uint32_t scratch[256];
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struct {
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unsigned mthd:16;
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unsigned inc:4;
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@ -96,68 +71,17 @@ load_params(struct mme_tu104_sim *sim,
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inst_loads_out(inst, MME_TU104_OUT_OP_LOAD1);
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assert(has_load0 || !has_load1);
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if (has_load0) {
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sim->load[0] = *sim->params;
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sim->params++;
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sim->param_count--;
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}
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if (has_load0)
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sim->load[0] = sim->state_ops->load(sim->state_handler);
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if (has_load1) {
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sim->load[1] = *sim->params;
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sim->params++;
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sim->param_count--;
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}
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if (has_load1)
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sim->load[1] = sim->state_ops->load(sim->state_handler);
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}
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static uint32_t
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load_state(struct mme_tu104_sim *sim, uint16_t state)
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{
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assert(state % 4 == 0);
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if (NVC597_SET_MME_SHADOW_SCRATCH(0) <= state &&
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state < NVC597_CALL_MME_MACRO(0)) {
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uint32_t i = (state - NVC597_SET_MME_SHADOW_SCRATCH(0)) / 4;
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assert(i <= ARRAY_SIZE(sim->scratch));
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return sim->scratch[i];
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}
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return 0;
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}
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static uint32_t *
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find_mem(struct mme_tu104_sim *sim, uint64_t addr, const char *op_desc)
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{
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for (uint32_t i = 0; i < sim->mem_count; i++) {
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if (addr < sim->mems[i].addr)
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continue;
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uint64_t offset = addr - sim->mems[i].addr;
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if (offset >= sim->mems[i].size)
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continue;
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assert(sim->mems[i].data != NULL);
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return (uint32_t *)((char *)sim->mems[i].data + offset);
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}
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fprintf(stderr, "FAULT in %s at address 0x%"PRIx64"\n", op_desc, addr);
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abort();
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}
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static void
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finish_dma_read_fifo(struct mme_tu104_sim *sim)
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{
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if (sim->dma.read_fifo.count == 0)
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return;
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for (uint32_t i = 0; i < sim->dma.read_fifo.count; i++) {
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uint32_t *src = find_mem(sim, sim->mem_addr + i * 4,
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"MME_DMA_READ_FIFOED");
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assert(src != NULL);
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sim->dma.read_fifo.data[i] = *src;
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}
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sim->param_count = sim->dma.read_fifo.count;
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sim->params = sim->dma.read_fifo.data;
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return sim->state_ops->state(sim->state_handler, state);
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}
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static void
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@ -166,50 +90,10 @@ flush_mthd(struct mme_tu104_sim *sim)
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if (!sim->mthd.has_mthd)
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return;
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uint16_t mthd = sim->mthd.mthd;
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const uint32_t *p = sim->mthd.data;
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const uint32_t *end = sim->mthd.data + sim->mthd.data_len;
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while (p < end) {
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uint32_t dw_used = 1;
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if (NVC597_SET_MME_SHADOW_SCRATCH(0) <= mthd &&
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mthd < NVC597_CALL_MME_MACRO(0)) {
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uint32_t i = (mthd - NVC597_SET_MME_SHADOW_SCRATCH(0)) / 4;
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assert(i <= ARRAY_SIZE(sim->scratch));
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sim->scratch[i] = *p;
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} else {
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switch (mthd) {
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case NVC597_SET_REPORT_SEMAPHORE_A: {
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assert(p + 4 <= end);
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uint64_t addr = ((uint64_t)p[0] << 32) | p[1];
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uint32_t data = p[2];
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assert(p[3] == 0x10000000);
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dw_used = 4;
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uint32_t *mem = find_mem(sim, addr, "SET_REPORT_SEMAPHORE");
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*mem = data;
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break;
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}
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case NVC597_SET_MME_DATA_RAM_ADDRESS:
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sim->ram.addr = *p;
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break;
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case NVC597_SET_MME_MEM_ADDRESS_A:
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assert(p + 2 <= end);
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sim->mem_addr = ((uint64_t)p[0] << 32) | p[1];
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dw_used = 2;
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break;
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case NVC597_MME_DMA_READ_FIFOED:
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sim->dma.read_fifo.count = *p;
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break;
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default:
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fprintf(stdout, "%s:\n", P_PARSE_NVC597_MTHD(mthd));
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P_DUMP_NVC597_MTHD_DATA(stdout, mthd, *p, " ");
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break;
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}
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}
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p += dw_used;
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assert(sim->mthd.inc == 1);
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mthd += dw_used * 4;
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for (uint32_t i = 0; i < sim->mthd.data_len; i++) {
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sim->state_ops->mthd(sim->state_handler,
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sim->mthd.mthd + (i * 4),
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sim->mthd.data[i]);
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}
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sim->mthd.has_mthd = false;
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@ -225,7 +109,8 @@ eval_extended(struct mme_tu104_sim *sim,
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assert(x == 0x1000);
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assert(y == 1);
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flush_mthd(sim);
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finish_dma_read_fifo(sim);
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if (sim->state_ops->barrier)
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sim->state_ops->barrier(sim->state_handler);
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}
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static uint32_t
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@ -458,16 +343,18 @@ eval_alu(struct mme_tu104_sim *sim,
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}
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break;
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}
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case MME_TU104_ALU_OP_DREAD:
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case MME_TU104_ALU_OP_DREAD: {
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assert(inst->alu[alu_idx].src[1] == MME_TU104_REG_ZERO);
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assert(x < ARRAY_SIZE(sim->ram.data));
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res = sim->ram.data[x];
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uint32_t *dram = sim->state_ops->map_dram(sim->state_handler, x);
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res = *dram;
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break;
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case MME_TU104_ALU_OP_DWRITE:
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}
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case MME_TU104_ALU_OP_DWRITE: {
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assert(inst->alu[alu_idx].dst == MME_TU104_REG_ZERO);
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assert(x < ARRAY_SIZE(sim->ram.data));
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sim->ram.data[x] = y;
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uint32_t *dram = sim->state_ops->map_dram(sim->state_handler, x);
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*dram = y;
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break;
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}
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default:
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unreachable("Unhandled ALU op");
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}
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@ -529,15 +416,13 @@ eval_out(struct mme_tu104_sim *sim,
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}
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void
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mme_tu104_sim(uint32_t inst_count, const struct mme_tu104_inst *insts,
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uint32_t param_count, const uint32_t *params,
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uint32_t mem_count, struct mme_tu104_sim_mem *mems)
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mme_tu104_sim_core(uint32_t inst_count, const struct mme_tu104_inst *insts,
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const struct mme_sim_state_ops *state_ops,
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void *state_handler)
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{
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struct mme_tu104_sim sim = {
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.param_count = param_count,
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.params = params,
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.mem_count = mem_count,
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.mems = mems,
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.state_ops = state_ops,
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.state_handler = state_handler,
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};
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bool end_next = false;
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@ -578,3 +463,192 @@ mme_tu104_sim(uint32_t inst_count, const struct mme_tu104_inst *insts,
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flush_mthd(&sim);
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}
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struct mme_tu104_state_sim {
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uint32_t param_count;
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const uint32_t *params;
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/* Bound memory ranges */
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uint32_t mem_count;
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struct mme_tu104_sim_mem *mems;
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/* SET_MME_MEM_ADDRESS_A/B */
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uint64_t mem_addr_lo;
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uint64_t mem_addr_hi;
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/* RAM, accessed by DREAD/DWRITE */
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struct {
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uint32_t data[MME_TU104_DRAM_COUNT];
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/* SET_MME_MEM_RAM_ADDRESS */
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uint32_t addr;
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} ram;
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struct {
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struct {
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uint32_t data[1024];
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uint32_t count;
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} read_fifo;
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} dma;
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/* NVC597_SET_MME_SHADOW_SCRATCH(i) */
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uint32_t scratch[MME_TU104_SCRATCH_COUNT];
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struct {
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uint32_t addr_hi;
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uint32_t addr_lo;
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uint32_t data;
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} report_sem;
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};
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static uint32_t *
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find_mem(struct mme_tu104_state_sim *sim, uint64_t addr, const char *op_desc)
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{
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for (uint32_t i = 0; i < sim->mem_count; i++) {
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if (addr < sim->mems[i].addr)
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continue;
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uint64_t offset = addr - sim->mems[i].addr;
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if (offset >= sim->mems[i].size)
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continue;
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assert(sim->mems[i].data != NULL);
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return (uint32_t *)((char *)sim->mems[i].data + offset);
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}
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fprintf(stderr, "FAULT in %s at address 0x%"PRIx64"\n", op_desc, addr);
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abort();
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}
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static uint32_t
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mme_tu104_state_sim_load(void *_sim)
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{
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struct mme_tu104_state_sim *sim = _sim;
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assert(sim->param_count > 0);
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uint32_t data = *sim->params;
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sim->params++;
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sim->param_count--;
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return data;
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}
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static uint32_t
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mme_tu104_state_sim_state(void *_sim, uint16_t addr)
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{
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struct mme_tu104_state_sim *sim = _sim;
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assert(addr % 4 == 0);
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if (NVC597_SET_MME_SHADOW_SCRATCH(0) <= addr &&
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addr < NVC597_CALL_MME_MACRO(0)) {
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uint32_t i = (addr - NVC597_SET_MME_SHADOW_SCRATCH(0)) / 4;
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assert(i <= ARRAY_SIZE(sim->scratch));
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return sim->scratch[i];
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}
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return 0;
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}
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static void
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mme_tu104_state_sim_mthd(void *_sim, uint16_t addr, uint32_t data)
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{
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struct mme_tu104_state_sim *sim = _sim;
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assert(addr % 4 == 0);
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switch (addr) {
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case NVC597_SET_REPORT_SEMAPHORE_A:
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sim->report_sem.addr_hi = data;
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break;
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case NVC597_SET_REPORT_SEMAPHORE_B:
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sim->report_sem.addr_lo = data;
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break;
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case NVC597_SET_REPORT_SEMAPHORE_C:
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sim->report_sem.data = data;
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break;
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case NVC597_SET_REPORT_SEMAPHORE_D: {
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assert(data == 0x10000000);
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uint64_t sem_report_addr =
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((uint64_t)sim->report_sem.addr_hi << 32) | sim->report_sem.addr_lo;
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uint32_t *mem = find_mem(sim, sem_report_addr, "SET_REPORT_SEMAPHORE");
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*mem = sim->report_sem.data;
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break;
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}
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case NVC597_SET_MME_DATA_RAM_ADDRESS:
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sim->ram.addr = data;
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break;
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case NVC597_SET_MME_MEM_ADDRESS_A:
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sim->mem_addr_hi = data;
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break;
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case NVC597_SET_MME_MEM_ADDRESS_B:
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sim->mem_addr_lo = data;
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break;
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case NVC597_MME_DMA_READ_FIFOED:
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sim->dma.read_fifo.count = data;
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break;
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default:
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if (NVC597_SET_MME_SHADOW_SCRATCH(0) <= addr &&
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addr < NVC597_CALL_MME_MACRO(0)) {
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uint32_t i = (addr - NVC597_SET_MME_SHADOW_SCRATCH(0)) / 4;
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assert(i <= ARRAY_SIZE(sim->scratch));
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sim->scratch[i] = data;
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} else {
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fprintf(stdout, "%s:\n", P_PARSE_NVC597_MTHD(addr));
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P_DUMP_NVC597_MTHD_DATA(stdout, addr, data, " ");
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}
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break;
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}
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}
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static void
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mme_tu104_state_sim_barrier(void *_sim)
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{
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struct mme_tu104_state_sim *sim = _sim;
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if (sim->dma.read_fifo.count == 0)
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return;
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const uint64_t mem_addr =
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((uint64_t)sim->mem_addr_hi << 32) | sim->mem_addr_lo;
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for (uint32_t i = 0; i < sim->dma.read_fifo.count; i++) {
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uint32_t *src = find_mem(sim, mem_addr + i * 4,
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"MME_DMA_READ_FIFOED");
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assert(src != NULL);
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sim->dma.read_fifo.data[i] = *src;
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}
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sim->param_count = sim->dma.read_fifo.count;
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sim->params = sim->dma.read_fifo.data;
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}
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static uint32_t *
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mme_tu104_state_sim_map_dram(void *_sim, uint32_t idx)
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{
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struct mme_tu104_state_sim *sim = _sim;
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assert(idx < ARRAY_SIZE(sim->ram.data));
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return &sim->ram.data[idx];
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}
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static const struct mme_sim_state_ops mme_tu104_state_sim_ops = {
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.load = mme_tu104_state_sim_load,
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.state = mme_tu104_state_sim_state,
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.mthd = mme_tu104_state_sim_mthd,
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.barrier = mme_tu104_state_sim_barrier,
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.map_dram = mme_tu104_state_sim_map_dram,
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};
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void
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mme_tu104_sim(uint32_t inst_count, const struct mme_tu104_inst *insts,
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uint32_t param_count, const uint32_t *params,
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uint32_t mem_count, struct mme_tu104_sim_mem *mems)
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{
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struct mme_tu104_state_sim state_sim = {
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.param_count = param_count,
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.params = params,
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.mem_count = mem_count,
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.mems = mems,
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};
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mme_tu104_sim_core(inst_count, insts, &mme_tu104_state_sim_ops, &state_sim);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -5,6 +5,8 @@
|
|||
#ifndef MME_TU104_SIM_H
|
||||
#define MME_TU104_SIM_H
|
||||
|
||||
#include "mme_sim.h"
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdlib.h>
|
||||
|
||||
|
|
@ -20,6 +22,10 @@ struct mme_tu104_sim_mem {
|
|||
size_t size;
|
||||
};
|
||||
|
||||
void mme_tu104_sim_core(uint32_t inst_count, const struct mme_tu104_inst *insts,
|
||||
const struct mme_sim_state_ops *state_ops,
|
||||
void *state_handler);
|
||||
|
||||
void mme_tu104_sim(uint32_t inst_count, const struct mme_tu104_inst *insts,
|
||||
uint32_t param_count, const uint32_t *params,
|
||||
uint32_t mem_count, struct mme_tu104_sim_mem *mems);
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue