fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-01-31 02:40:25 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 3
184774 commits 66 branches 919 tags 976 MiB
Commit graph

184774 commits

This branch
This branch
All branches
Author SHA1 Message Date
Faith Ekstrand
abe52a6d03 nvk: Re-structure early shader compilation a bit 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25443>
 2023-09-28 03:55:53 +00:00
Faith Ekstrand
a4f8fd9dd5 nvk: Hook up the disk cache 
This won't actually do much yet because we don't have pipeline caches
yet but it turns on the infrastructure.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25443>
 2023-09-28 03:55:53 +00:00
Faith Ekstrand
d08df319ca nvk: Store a 20-bit driver_build_sha in nvk_instance 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25443>
 2023-09-28 03:55:53 +00:00
Timothy Arceri
1780102923 nir: fix typo in comment 
The variable is unused or dead, not used.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25414>
 2023-09-28 01:54:43 +00:00
antonino
76d150674b vulkan: Handle vkSetDebugUtilsObjectNameEXT on WSI objects 
Some WSI objects don't extend `vk_object_base` therefore they need
special handling.

Fixes: 3c87618d35 ("vulkan: Handle vkGet/SetPrivateDataEXT on Android swapchains")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24752>
 2023-09-28 01:23:55 +00:00
antonino
5fe289d741 vulkan: Extend vkGet/SetPrivateDataEXT handling to VkSurface 
VkSurface is handled by WSI and it doesn't extend `vk_object_base` so it
needs special handling.

Fixes: 3c87618d35 ("vulkan: Handle vkGet/SetPrivateDataEXT on Android swapchains")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24752>
 2023-09-28 01:23:55 +00:00
antonino
710d478066 vulkan: Extend vkGet/SetPrivateDataEXT handling to all platforms 
Non-android platforms use mesa WSI, however some WSI object still don't
extend `vk_object_base` so they still need special handling.

Fixes: 3c87618d35 ("vulkan: Handle vkGet/SetPrivateDataEXT on Android swapchains")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24752>
 2023-09-28 01:23:55 +00:00
Dave Airlie
c45ae052f0 llvmpipe/cs: migrate cs image handle to common jit code. 
This moves some of the code over, and uses the generic paths.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25416>
 2023-09-28 00:41:04 +00:00
Dave Airlie
2c74f825f4 llvmpipe/cs: migrate to generic jit texture from pipe code. 
This moves some cs specific bits to the generic code and uses it.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25416>
 2023-09-28 00:41:04 +00:00
Marcin Ślusarz
ea92bd8d44 intel/compiler: mask GS URB handles at thread payload construction 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
 2023-09-27 23:57:25 +00:00
Marcin Ślusarz
815eee10e0 intel/compiler/mesh: implement IO for xe2 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
 2023-09-27 23:57:25 +00:00
Marcin Ślusarz
ee4214de6e intel/compiler/mesh: fix position of output URB handle for xe2 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
 2023-09-27 23:57:25 +00:00
Francisco Jerez
7f3dc4505d intel/fs: Delete manual 'inst->mlen' calculations from all uses of logical URB reads. 
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
 2023-09-27 23:57:25 +00:00
Francisco Jerez
53d1d793cb intel/fs: Delete manual 'inst->mlen' calculations from all uses of logical URB writes. 
Rework:
 * Marcin: update emit_urb_indirect_vec4_write

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
 2023-09-27 23:57:25 +00:00
Francisco Jerez
34a2c9ce35 intel/fs: Specify number of data components of logical URB writes via control immediate. 
This is what most logical SEND messages do when they take a variable
number of components.  'inst->mlen' is expected to be zero for logical
SEND opcodes, which are expected to behave like plain arithmetic
operations, so certain automated transformations (like SIMD lowering)
can manipulate them without opcode-specific special-casing.

Guessing the number of components from 'inst->mlen' has other
disadvantages, because it requires duplicating the logic that infers
the message payload size in every use of the instruction -- Instead we
can just do the computation once during logical send lowering.  In
addition on LNL platform this causes the 'inst->mlen' field of URB
writes to have units inconsistent with every other SEND instruction,
which is likely to lead to confusion and bugs down the road.

Rework:
 * Marcin: update emit_urb_indirect_vec4_write

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
 2023-09-27 23:57:25 +00:00
Francisco Jerez
74c9973c0b intel/fs/xe2+: Fix URB writes with 0 data components. 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
 2023-09-27 23:57:25 +00:00
Caio Oliveira
c89597085a intel/compiler/xe2: Update TCS ICP handle code to support SIMD16 
Rework:
 * Use ffs(grf_size_bytes) (s-b Ken)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
 2023-09-27 23:57:25 +00:00
Caio Oliveira
f0fcb778b4 intel/compiler/xe2: Fix URB writes in TCS 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
 2023-09-27 23:57:25 +00:00
Caio Oliveira
0c03018abf intel/compiler/xe2: URB fence uses LSC now 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
 2023-09-27 23:57:25 +00:00
Ian Romanick
623465e26d intel/compiler/xe2: Update fs_visitor::emit_urb_writes to not assume SIMD8 
v2: Account for 512b physical registers which causes the URB handle to be in FIXED_GFR 2 instead of 1.

XXX - Use fs_builder::vgrf() instead of open-coded dispatch_width calculations.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
 2023-09-27 23:57:25 +00:00
Kenneth Graunke
4fffdbbfa2 intel/fs: Fix Xe2 URB read/lowering with per-slot offsets 
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
 2023-09-27 23:57:25 +00:00
Jordan Justen
c28539a2fe intel/compiler: Use enum xe2_lsc_cache_load on xe2 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
 2023-09-27 23:57:25 +00:00
Jordan Justen
8d27b327f2 intel/compiler: Add enum xe2_lsc_cache_load 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
 2023-09-27 23:57:25 +00:00
Jordan Justen
09fc9ff114 intel/compiler: Use enum xe2_lsc_cache_store on xe2 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
 2023-09-27 23:57:25 +00:00
Jordan Justen
c54eff2e03 intel/compiler: Add enum xe2_lsc_cache_store 
Rework:
 * Rohan: Fix enum value for L1WB_L3WB
 * Fix write-through comments (Ken)

Ref: bspec 71167
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
 2023-09-27 23:57:25 +00:00
Marcin Ślusarz
1245020282 intel/compiler: add initial support for URB_LOGICAL_SRC_CHANNEL_MASK to lower_urb_write_logical_send_xe2 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
 2023-09-27 23:57:25 +00:00
Marcin Ślusarz
9c90377962 intel/compiler: add lsc_msg_desc_wcmask 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
 2023-09-27 23:57:25 +00:00
Ian Romanick
feec9166cd intel/compiler/xe2: Handle new URB write messages 
Rework:
 * idr v1: Fix compilation error.
 * idr v2: Add support for per-channel offsets.
 * idr v3: get_lowered_simd_width is 16 on Xe2+.
 * idr v4: Add disassembly support.  Add validation support.
 * Sqaushed in changes Marcin Ślusarz's patches:
   * "intel/compiler: skip adding 0 to payload address"
   * "intel/compiler/xe2: drop masking off top 8 bits of URB handle"

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
 2023-09-27 23:57:25 +00:00
Ian Romanick
fa53a7d241 intel/compiler/xe2: Handle new URB read messages 
Rework:
 * Sqaushed in changes Marcin Ślusarz's patches:
   * "intel/compiler: skip adding 0 to payload address"
   * "intel/compiler/xe2: drop masking off top 8 bits of URB handle"

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
 2023-09-27 23:57:25 +00:00
Konstantin Seurer
4552e594f1 vulkan: Remove vk_get_physical_device_core_1_*_feature_ext 
It's unused.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24773>
 2023-09-27 23:02:29 +00:00
Konstantin Seurer
05796b29f5 hasvk: Use the common GetPhysicalDeviceFeatures2 implementation 
Reviewed-by: Julia Tatz <tatz.j@northeastern.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24773>
 2023-09-27 23:02:29 +00:00
Rhys Perry
65afc8bebf nir/algebraic: optimize u2u32(a >> 32) 
fossil-db (navi21):
Totals from 352 (0.44% of 79330) affected shaders:
Instrs: 271816 -> 271240 (-0.21%); split: -0.28%, +0.07%
CodeSize: 1546520 -> 1544448 (-0.13%); split: -0.23%, +0.09%
SpillVGPRs: 832 -> 827 (-0.60%); split: -1.08%, +0.48%
Latency: 4037120 -> 4021748 (-0.38%); split: -0.41%, +0.03%
InvThroughput: 1369540 -> 1362066 (-0.55%); split: -0.59%, +0.04%
VClause: 6476 -> 6471 (-0.08%); split: -0.12%, +0.05%
SClause: 6798 -> 6794 (-0.06%)
Copies: 44828 -> 44630 (-0.44%); split: -0.89%, +0.45%
Branches: 8845 -> 8844 (-0.01%); split: -0.05%, +0.03%
PreSGPRs: 14684 -> 14659 (-0.17%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25409>
 2023-09-27 22:13:01 +00:00
Rhys Perry
bcdac65ca3 nir/lower_int64: fix find_lsb(0) 
If the high 32 bits were zero, this would be umin(find_lsb(lo), 31). This
evaluates to 31 if lo is also zero, instead of -1.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Fixes: 9293d8e64b ("nir: Add find_lsb lowering to nir_lower_int64.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25409>
 2023-09-27 22:13:01 +00:00
wangra
e90f9d8e21 tu/kgsl: Fix bitfield of DITHER_MODE_MRT6 
The enum `adreno_rb_dither_mode` needs 2 bits, change the `high` to 13 to make sure 2 bits are used for `DITHER_MODE_MRT6`

Fixes: e03259974e ("freedreno: Generate headers from xml files")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25439>
 2023-09-27 21:45:40 +00:00
Jordan Justen
b5eb96384c anv: Print warning that Xe2 is not supported rather than failing 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25411>
 2023-09-27 21:11:18 +00:00
Jordan Justen
30ba269070 anv: Build for Xe2 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25411>
 2023-09-27 21:11:18 +00:00
Jordan Justen
65684b0c7f anv: Disable Ray Tracing on xe2 until our compiler supports Xe2 RT 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25411>
 2023-09-27 21:11:18 +00:00
Jordan Justen
3f1b4dd434 anv/blorp: Use anv_genX to set device->blorp.exec 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25411>
 2023-09-27 21:11:18 +00:00
Jordan Justen
3bb96643f7 iris: Build for Xe2 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25411>
 2023-09-27 21:11:18 +00:00
Lionel Landwerlin
ee4062666c iris: add missing workaround for 3DSTATE_LINE_STIPPLE 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25425>
 2023-09-27 20:32:50 +00:00
Lionel Landwerlin
a28ff995bb anv: add missing workaround for 3DSTATE_LINE_STIPPLE 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25425>
 2023-09-27 20:32:50 +00:00
Lionel Landwerlin
c59179e6bb anv/iris: widen Wa_14015946265 to Gfx11+ 
We missed out that ICL+ added a programming requiring a CS_STALL.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25426>
 2023-09-27 19:56:24 +00:00
Connor Abbott
302907e347 tu: Expose VK_KHR_maintenance5 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25001>
 2023-09-27 19:07:22 +00:00
Connor Abbott
b0f1cb8f31 freedreno/ci: Skip dEQP-VK.info.device_extensions 
Copied from anv and radv.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25001>
 2023-09-27 19:07:22 +00:00
Connor Abbott
e7d4bc6095 tu: Add maintenance5 properties 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25001>
 2023-09-27 19:07:22 +00:00
Connor Abbott
a86f2132b3 tu: Check for DEVICE_LOST in vkGetEventStatus() 
Required by maintenance5.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25001>
 2023-09-27 19:07:22 +00:00
Connor Abbott
b14a8dc2a7 tu: Support VkPipelineCreateFlags2CreateInfoKHR 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25001>
 2023-09-27 19:07:22 +00:00
Connor Abbott
53dbfab87b tu: Use new buffer usage flags 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25001>
 2023-09-27 19:07:22 +00:00
Connor Abbott
4fd12a18db tu: Implement vkGetRenderingAreaGranularityKHR 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25001>
 2023-09-27 19:07:22 +00:00
Connor Abbott
2fb42fbd42 tu: Implement vkGetImageSubresourceLayout2KHR and vkGetDeviceImageSubresourceLayoutKHR 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25001>
 2023-09-27 19:07:22 +00:00