fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2025-12-25 19:30:11 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions

intel/fs/xe2+: Fix URB writes with 0 data components.

Browse source 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
This commit is contained in:
Francisco Jerez 2022-09-28 17:10:25 -07:00 • committed by Marge Bot
parent c89597085a
commit 74c9973c0b
1 changed files with 3 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

5
src/intel/compiler/brw_lower_logical_sends.cpp
View file

@ -200,10 +200,11 @@ lower_urb_write_logical_send_xe2(const fs_builder &bld, fs_inst *inst)
/* Get the logical send arguments. */
const fs_reg handle = inst->src[URB_LOGICAL_SRC_HANDLE];
const fs_reg src = inst->src[URB_LOGICAL_SRC_DATA];
const fs_reg src = inst->components_read(URB_LOGICAL_SRC_DATA) ?
inst->src[URB_LOGICAL_SRC_DATA] : fs_reg(brw_imm_ud(0));
/* Calculate the total number of components of the payload. */
const unsigned src_comps = inst->components_read(URB_LOGICAL_SRC_DATA);
const unsigned src_comps = MAX2(1, inst->components_read(URB_LOGICAL_SRC_DATA));
const unsigned src_sz = type_sz(src.type);
fs_reg payload = bld.vgrf(BRW_REGISTER_TYPE_UD);