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intel/fs: Fix Xe2 URB read/lowering with per-slot offsets
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
This commit is contained in:
Kenneth Graunke
Marge Bot
parent
c28539a2fe
commit
4fffdbbfa2
1 changed files with 81 additions and 226 deletions
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@ -86,7 +86,6 @@ lower_urb_read_logical_send_xe2(const fs_builder &bld, fs_inst *inst)
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/* Get the logical send arguments. */
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const fs_reg handle = inst->src[URB_LOGICAL_SRC_HANDLE];
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const fs_reg dst = inst->dst;
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/* Calculate the total number of components of the payload. */
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const unsigned dst_comps = inst->size_written / (REG_SIZE * reg_unit(devinfo));
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@ -96,121 +95,48 @@ lower_urb_read_logical_send_xe2(const fs_builder &bld, fs_inst *inst)
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bld.MOV(payload, handle);
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/* The low 24-bits of the URB handle is a byte offset into the URB area.
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* Add the offset of the write to this value.
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*
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* FINISHME: What units is inst->offset? vec4, right?
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* Add the (OWord) offset of the write to this value.
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*/
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if (inst->offset) {
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bld.ADD(payload, payload, brw_imm_ud(inst->offset * 16));
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inst->offset = 0;
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}
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if (inst->src[URB_LOGICAL_SRC_PER_SLOT_OFFSETS].file != BAD_FILE) {
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fs_reg offsets = inst->src[URB_LOGICAL_SRC_PER_SLOT_OFFSETS];
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fs_reg payload1 = bld.vgrf(BRW_REGISTER_TYPE_UD);
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fs_reg tmp_dst = bld.vgrf(BRW_REGISTER_TYPE_UD);
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for (unsigned i = 1; i < dst_comps; i++) {
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bld.ADD(payload1, payload, offset(offsets, bld, i - 1));
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fs_inst *send = bld.emit(SHADER_OPCODE_SEND,
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bld.null_reg_ud(),
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brw_imm_ud(0) /* desc */,
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brw_imm_ud(0) /* ex_desc */,
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brw_vec8_grf(0, 0) /* payload */);
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bld.MOV(offset(dst, bld, i - 1), tmp_dst);
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send->sfid = BRW_SFID_URB;
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send->desc = lsc_msg_desc(devinfo, LSC_OP_LOAD, send->exec_size,
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LSC_ADDR_SURFTYPE_FLAT, LSC_ADDR_SIZE_A32,
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1 /* num_coordinates */,
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LSC_DATA_SIZE_D32, 1 /* num_channels */,
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false /* transpose */,
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LSC_CACHE_STORE_L1UC_L3UC,
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false /* has_dest */);
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send->mlen = lsc_msg_desc_src0_len(devinfo, send->desc);
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send->ex_mlen = 0;
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send->header_size = 0;
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send->send_has_side_effects = false;
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send->send_is_volatile = true;
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send->resize_sources(4);
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send->dst = tmp_dst;
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send->src[0] = brw_imm_ud(0);
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send->src[1] = brw_imm_ud(0);
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send->src[2] = payload1;
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send->src[3] = brw_null_reg();
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}
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bld.ADD(payload1, payload, offset(offsets, bld, dst_comps - 1));
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/* Insert the MOV after the send because it reads the register written
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* by the send.
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*/
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bld.at(NULL, inst->next).MOV(offset(dst, bld, dst_comps - 1), tmp_dst);
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inst->sfid = BRW_SFID_URB;
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inst->desc = lsc_msg_desc(devinfo, LSC_OP_LOAD, inst->exec_size,
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LSC_ADDR_SURFTYPE_FLAT, LSC_ADDR_SIZE_A32,
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1 /* num_coordinates */,
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LSC_DATA_SIZE_D32, 1 /* num_channels */,
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false /* transpose */,
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LSC_CACHE_STORE_L1UC_L3UC,
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false /* has_dest */);
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/* Update the original instruction. */
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inst->opcode = SHADER_OPCODE_SEND;
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inst->mlen = lsc_msg_desc_src0_len(devinfo, inst->desc);
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inst->ex_mlen = 0;
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inst->header_size = 0;
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inst->send_has_side_effects = false;
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inst->send_is_volatile = true;
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inst->resize_sources(4);
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inst->dst = tmp_dst;
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inst->src[0] = brw_imm_ud(0);
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inst->src[1] = brw_imm_ud(0);
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inst->src[2] = payload1;
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inst->src[3] = brw_null_reg();
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} else {
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inst->sfid = BRW_SFID_URB;
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assert((dst_comps >= 1 && dst_comps <= 4) || dst_comps == 8);
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inst->desc = lsc_msg_desc(devinfo, LSC_OP_LOAD, inst->exec_size,
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LSC_ADDR_SURFTYPE_FLAT, LSC_ADDR_SIZE_A32,
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1 /* num_coordinates */,
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LSC_DATA_SIZE_D32, dst_comps /* num_channels */,
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false /* transpose */,
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LSC_CACHE_STORE_L1UC_L3UC,
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false /* has_dest */);
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/* Update the original instruction. */
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inst->opcode = SHADER_OPCODE_SEND;
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inst->mlen = lsc_msg_desc_src0_len(devinfo, inst->desc);
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inst->ex_mlen = 0;
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inst->header_size = 0;
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inst->send_has_side_effects = true;
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inst->send_is_volatile = false;
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inst->resize_sources(4);
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inst->src[0] = brw_imm_ud(0);
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inst->src[1] = brw_imm_ud(0);
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inst->src[2] = payload;
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inst->src[3] = brw_null_reg();
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fs_reg offsets = inst->src[URB_LOGICAL_SRC_PER_SLOT_OFFSETS];
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if (offsets.file != BAD_FILE) {
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fs_reg offsets_B = bld.vgrf(BRW_REGISTER_TYPE_UD);
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bld.SHL(offsets_B, offsets, brw_imm_ud(4)); /* OWords -> Bytes */
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bld.ADD(payload, payload, offsets_B);
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}
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inst->sfid = BRW_SFID_URB;
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assert((dst_comps >= 1 && dst_comps <= 4) || dst_comps == 8);
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inst->desc = lsc_msg_desc(devinfo, LSC_OP_LOAD, inst->exec_size,
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LSC_ADDR_SURFTYPE_FLAT, LSC_ADDR_SIZE_A32,
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1 /* num_coordinates */,
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LSC_DATA_SIZE_D32, dst_comps /* num_channels */,
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false /* transpose */,
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LSC_CACHE(devinfo, STORE, L1UC_L3UC),
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false /* has_dest */);
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/* Update the original instruction. */
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inst->opcode = SHADER_OPCODE_SEND;
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inst->mlen = lsc_msg_desc_src0_len(devinfo, inst->desc);
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inst->ex_mlen = 0;
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inst->header_size = 0;
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inst->send_has_side_effects = true;
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inst->send_is_volatile = false;
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inst->resize_sources(4);
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inst->src[0] = brw_imm_ud(0);
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inst->src[1] = brw_imm_ud(0);
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inst->src[2] = payload;
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inst->src[3] = brw_null_reg();
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}
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static void
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@ -285,130 +211,59 @@ lower_urb_write_logical_send_xe2(const fs_builder &bld, fs_inst *inst)
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bld.MOV(payload, handle);
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/* The low 24-bits of the URB handle is a byte offset into the URB area.
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* Add the offset of the write to this value.
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*
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* FINISHME: What units is inst->offset? vec4, right?
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* Add the (OWord) offset of the write to this value.
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*/
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if (inst->offset) {
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bld.ADD(payload, payload, brw_imm_ud(inst->offset * 16));
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inst->offset = 0;
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}
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if (inst->src[URB_LOGICAL_SRC_PER_SLOT_OFFSETS].file != BAD_FILE) {
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/* FINISHME: This is not yet implemented. */
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assert(inst->src[URB_LOGICAL_SRC_CHANNEL_MASK].file == BAD_FILE);
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fs_reg offsets = inst->src[URB_LOGICAL_SRC_PER_SLOT_OFFSETS];
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fs_reg payload1 = bld.vgrf(BRW_REGISTER_TYPE_UD);
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fs_reg payload2 = bld.vgrf(BRW_REGISTER_TYPE_UD);
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for (unsigned i = 1; i < src_comps; i++) {
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bld.MOV(payload2, offset(src, bld, i - 1));
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bld.ADD(payload1, payload, offset(offsets, bld, i - 1));
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fs_inst *send = bld.emit(SHADER_OPCODE_SEND,
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bld.null_reg_ud(),
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brw_imm_ud(0) /* desc */,
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brw_imm_ud(0) /* ex_desc */,
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brw_vec8_grf(0, 0) /* payload */);
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const unsigned ex_mlen = (src_sz * inst->exec_size) / REG_SIZE;
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send->sfid = BRW_SFID_URB;
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send->desc = lsc_msg_desc(devinfo, LSC_OP_STORE, send->exec_size,
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LSC_ADDR_SURFTYPE_FLAT, LSC_ADDR_SIZE_A32,
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1 /* num_coordinates */,
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LSC_DATA_SIZE_D32, 1 /* num_channels */,
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false /* transpose */,
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LSC_CACHE_STORE_L1UC_L3UC,
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false /* has_dest */);
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send->mlen = lsc_msg_desc_src0_len(devinfo, send->desc);
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send->ex_mlen = ex_mlen;
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send->header_size = 0;
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send->send_has_side_effects = true;
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send->send_is_volatile = false;
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send->resize_sources(4);
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send->src[0] = brw_imm_ud(0);
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send->src[1] = brw_imm_ud(0);
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send->src[2] = payload1;
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send->src[3] = payload2;
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}
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bld.MOV(payload2, offset(src, bld, src_comps - 1));
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bld.ADD(payload1, payload, offset(offsets, bld, src_comps - 1));
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const unsigned ex_mlen = (src_sz * inst->exec_size) / REG_SIZE;
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inst->sfid = BRW_SFID_URB;
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inst->desc = lsc_msg_desc(devinfo, LSC_OP_STORE, inst->exec_size,
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LSC_ADDR_SURFTYPE_FLAT, LSC_ADDR_SIZE_A32,
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1 /* num_coordinates */,
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LSC_DATA_SIZE_D32, 1 /* num_channels */,
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false /* transpose */,
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LSC_CACHE_STORE_L1UC_L3UC,
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false /* has_dest */);
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/* Update the original instruction. */
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inst->opcode = SHADER_OPCODE_SEND;
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inst->mlen = lsc_msg_desc_src0_len(devinfo, inst->desc);
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inst->ex_mlen = ex_mlen;
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inst->header_size = 0;
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inst->send_has_side_effects = true;
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inst->send_is_volatile = false;
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inst->resize_sources(4);
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inst->src[0] = brw_imm_ud(0);
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inst->src[1] = brw_imm_ud(0);
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inst->src[2] = payload1;
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inst->src[3] = payload2;
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} else {
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const fs_reg cmask = inst->src[URB_LOGICAL_SRC_CHANNEL_MASK];
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unsigned mask = 0;
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if (cmask.file != BAD_FILE) {
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assert(cmask.file == IMM);
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assert(cmask.type == BRW_REGISTER_TYPE_UD);
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mask = cmask.ud >> 16;
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}
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fs_reg payload2 = bld.move_to_vgrf(src, src_comps);
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const unsigned ex_mlen = (src_comps * src_sz * inst->exec_size) / REG_SIZE;
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inst->sfid = BRW_SFID_URB;
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enum lsc_opcode op = mask ? LSC_OP_STORE_CMASK : LSC_OP_STORE;
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inst->desc = lsc_msg_desc_wcmask(devinfo, op, inst->exec_size,
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LSC_ADDR_SURFTYPE_FLAT, LSC_ADDR_SIZE_A32,
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1 /* num_coordinates */,
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LSC_DATA_SIZE_D32, src_comps /* num_channels */,
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false /* transpose */,
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LSC_CACHE_STORE_L1UC_L3UC,
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false /* has_dest */, mask);
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/* Update the original instruction. */
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inst->opcode = SHADER_OPCODE_SEND;
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inst->mlen = lsc_msg_desc_src0_len(devinfo, inst->desc);
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inst->ex_mlen = ex_mlen;
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inst->header_size = 0;
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inst->send_has_side_effects = true;
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inst->send_is_volatile = false;
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inst->resize_sources(4);
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inst->src[0] = brw_imm_ud(0);
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inst->src[1] = brw_imm_ud(0);
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inst->src[2] = payload;
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inst->src[3] = payload2;
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fs_reg offsets = inst->src[URB_LOGICAL_SRC_PER_SLOT_OFFSETS];
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if (offsets.file != BAD_FILE) {
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fs_reg offsets_B = bld.vgrf(BRW_REGISTER_TYPE_UD);
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bld.SHL(offsets_B, offsets, brw_imm_ud(4)); /* OWords -> Bytes */
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bld.ADD(payload, payload, offsets_B);
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}
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const fs_reg cmask = inst->src[URB_LOGICAL_SRC_CHANNEL_MASK];
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unsigned mask = 0;
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if (cmask.file != BAD_FILE) {
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assert(cmask.file == IMM);
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assert(cmask.type == BRW_REGISTER_TYPE_UD);
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mask = cmask.ud >> 16;
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}
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fs_reg payload2 = bld.move_to_vgrf(src, src_comps);
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const unsigned ex_mlen = (src_comps * src_sz * inst->exec_size) / REG_SIZE;
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inst->sfid = BRW_SFID_URB;
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enum lsc_opcode op = mask ? LSC_OP_STORE_CMASK : LSC_OP_STORE;
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inst->desc = lsc_msg_desc_wcmask(devinfo, op, inst->exec_size,
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LSC_ADDR_SURFTYPE_FLAT, LSC_ADDR_SIZE_A32,
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1 /* num_coordinates */,
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LSC_DATA_SIZE_D32, src_comps /* num_channels */,
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false /* transpose */,
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LSC_CACHE(devinfo, STORE, L1UC_L3UC),
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false /* has_dest */, mask);
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/* Update the original instruction. */
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inst->opcode = SHADER_OPCODE_SEND;
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inst->mlen = lsc_msg_desc_src0_len(devinfo, inst->desc);
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inst->ex_mlen = ex_mlen;
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inst->header_size = 0;
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inst->send_has_side_effects = true;
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inst->send_is_volatile = false;
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inst->resize_sources(4);
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inst->src[0] = brw_imm_ud(0);
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inst->src[1] = brw_imm_ud(0);
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inst->src[2] = payload;
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inst->src[3] = payload2;
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}
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static void
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