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anv/iris: widen Wa_14015946265 to Gfx11+

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We missed out that ICL+ added a programming requiring a CS_STALL.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25426>
This commit is contained in:
Lionel Landwerlin 2023-09-27 15:53:25 +03:00 • committed by Marge Bot
parent 302907e347
commit c59179e6bb
2 changed files with 18 additions and 4 deletions
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11
src/gallium/drivers/iris/iris_state.c
View file

@ -7003,8 +7003,15 @@ iris_upload_dirty_render_state(struct iris_context *ice,
ice->state.streamout + GENX(3DSTATE_STREAMOUT_length);
iris_batch_emit(batch, decl_list, 4 * ((decl_list[0] & 0xff) + 2));
#if GFX_VERx10 == 125
/* Wa_14015946265: Send PC with CS stall after SO_DECL. */
#if GFX_VER >= 11
/* ICL PRMs, Volume 2a - Command Reference: Instructions,
* 3DSTATE_SO_DECL_LIST:
*
* "Workaround: This command must be followed by a PIPE_CONTROL
* with CS Stall bit set."
*
* On DG2+ also known as Wa_1509820217.
*/
iris_emit_pipe_control_flush(batch,
"workaround: cs stall after so_decl",
PIPE_CONTROL_CS_STALL);

11
src/intel/vulkan/genX_gfx_state.c
View file

@ -1202,8 +1202,15 @@ genX(cmd_buffer_flush_gfx_hw_state)(struct anv_cmd_buffer *cmd_buffer)
anv_batch_emit_pipeline_state(&cmd_buffer->batch, pipeline,
final.so_decl_list);
#if GFX_VERx10 == 125
/* Wa_14015946265: Send PC with CS stall after SO_DECL. */
#if GFX_VER >= 11
/* ICL PRMs, Volume 2a - Command Reference: Instructions,
* 3DSTATE_SO_DECL_LIST:
*
* "Workaround: This command must be followed by a PIPE_CONTROL with
* CS Stall bit set."
*
* On DG2+ also known as Wa_1509820217.
*/
genx_batch_emit_pipe_control(&cmd_buffer->batch, device->info,
ANV_PIPE_CS_STALL_BIT);
#endif