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intel/compiler/mesh: implement IO for xe2
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
This commit is contained in:
Marcin Ślusarz
Marge Bot
parent
ee4214de6e
commit
815eee10e0
1 changed files with 219 additions and 5 deletions
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@ -1699,6 +1699,68 @@ emit_urb_direct_writes(const fs_builder &bld, nir_intrinsic_instr *instr,
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comp_shift, comps, mask);
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}
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static void
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emit_urb_direct_vec4_write_xe2(const fs_builder &bld,
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unsigned offset_in_bytes,
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const fs_reg &src,
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fs_reg urb_handle,
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unsigned comps,
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unsigned mask)
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{
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const struct intel_device_info *devinfo = bld.shader->devinfo;
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const unsigned runit = reg_unit(devinfo);
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const unsigned write_size = 8 * runit;
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if (offset_in_bytes > 0) {
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fs_builder bldall = bld.group(write_size, 0).exec_all();
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fs_reg new_handle = bldall.vgrf(BRW_REGISTER_TYPE_UD);
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bldall.ADD(new_handle, urb_handle, brw_imm_ud(offset_in_bytes));
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urb_handle = new_handle;
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}
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for (unsigned q = 0; q < bld.dispatch_width() / write_size; q++) {
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fs_builder hbld = bld.group(write_size, q);
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fs_reg payload_srcs[comps];
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for (unsigned c = 0; c < comps; c++)
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payload_srcs[c] = horiz_offset(offset(src, bld, c), write_size * q);
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fs_reg srcs[URB_LOGICAL_NUM_SRCS];
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srcs[URB_LOGICAL_SRC_HANDLE] = urb_handle;
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srcs[URB_LOGICAL_SRC_CHANNEL_MASK] = brw_imm_ud(mask << 16);
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int nr = bld.shader->alloc.allocate(comps * runit);
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srcs[URB_LOGICAL_SRC_DATA] = fs_reg(VGRF, nr, BRW_REGISTER_TYPE_F);
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srcs[URB_LOGICAL_SRC_COMPONENTS] = brw_imm_ud(comps);
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hbld.LOAD_PAYLOAD(srcs[URB_LOGICAL_SRC_DATA], payload_srcs, comps, 0);
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hbld.emit(SHADER_OPCODE_URB_WRITE_LOGICAL,
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reg_undef, srcs, ARRAY_SIZE(srcs));
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}
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}
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static void
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emit_urb_direct_writes_xe2(const fs_builder &bld, nir_intrinsic_instr *instr,
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const fs_reg &src, fs_reg urb_handle)
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{
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assert(nir_src_bit_size(instr->src[0]) == 32);
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nir_src *offset_nir_src = nir_get_io_offset_src(instr);
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assert(nir_src_is_const(*offset_nir_src));
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const unsigned comps = nir_src_num_components(instr->src[0]);
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assert(comps <= 4);
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const unsigned offset_in_dwords = nir_intrinsic_base(instr) +
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nir_src_as_uint(*offset_nir_src) +
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component_from_intrinsic(instr);
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const unsigned mask = nir_intrinsic_write_mask(instr);
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emit_urb_direct_vec4_write_xe2(bld, offset_in_dwords * 4, src,
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urb_handle, comps, mask);
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}
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static void
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emit_urb_indirect_vec4_write(const fs_builder &bld,
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const fs_reg &offset_src,
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@ -1764,6 +1826,57 @@ emit_urb_indirect_writes_mod(const fs_builder &bld, nir_intrinsic_instr *instr,
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urb_handle, comp_shift, comps, mask);
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}
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static void
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emit_urb_indirect_writes_xe2(const fs_builder &bld, nir_intrinsic_instr *instr,
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const fs_reg &src, const fs_reg &offset_src,
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fs_reg urb_handle)
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{
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assert(nir_src_bit_size(instr->src[0]) == 32);
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const struct intel_device_info *devinfo = bld.shader->devinfo;
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const unsigned runit = reg_unit(devinfo);
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const unsigned write_size = 8 * runit;
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const unsigned comps = nir_src_num_components(instr->src[0]);
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assert(comps <= 4);
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const unsigned base_in_dwords = nir_intrinsic_base(instr) +
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component_from_intrinsic(instr);
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if (base_in_dwords > 0) {
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fs_builder bldall = bld.group(write_size, 0).exec_all();
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fs_reg new_handle = bldall.vgrf(BRW_REGISTER_TYPE_UD);
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bldall.ADD(new_handle, urb_handle, brw_imm_ud(base_in_dwords * 4));
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urb_handle = new_handle;
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}
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const unsigned mask = nir_intrinsic_write_mask(instr);
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for (unsigned q = 0; q < bld.dispatch_width() / write_size; q++) {
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fs_builder wbld = bld.group(write_size, q);
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fs_reg payload_srcs[comps];
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for (unsigned c = 0; c < comps; c++)
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payload_srcs[c] = horiz_offset(offset(src, bld, c), write_size * q);
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fs_reg addr = wbld.vgrf(BRW_REGISTER_TYPE_UD);
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wbld.SHL(addr, horiz_offset(offset_src, write_size * q), brw_imm_ud(2));
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wbld.ADD(addr, addr, urb_handle);
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fs_reg srcs[URB_LOGICAL_NUM_SRCS];
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srcs[URB_LOGICAL_SRC_HANDLE] = addr;
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srcs[URB_LOGICAL_SRC_CHANNEL_MASK] = brw_imm_ud(mask << 16);
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int nr = bld.shader->alloc.allocate(comps * runit);
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srcs[URB_LOGICAL_SRC_DATA] = fs_reg(VGRF, nr, BRW_REGISTER_TYPE_F);
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srcs[URB_LOGICAL_SRC_COMPONENTS] = brw_imm_ud(comps);
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wbld.LOAD_PAYLOAD(srcs[URB_LOGICAL_SRC_DATA], payload_srcs, comps, 0);
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wbld.emit(SHADER_OPCODE_URB_WRITE_LOGICAL,
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reg_undef, srcs, ARRAY_SIZE(srcs));
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}
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}
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static void
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emit_urb_indirect_writes(const fs_builder &bld, nir_intrinsic_instr *instr,
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const fs_reg &src, const fs_reg &offset_src,
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@ -1872,6 +1985,46 @@ emit_urb_direct_reads(const fs_builder &bld, nir_intrinsic_instr *instr,
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}
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}
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static void
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emit_urb_direct_reads_xe2(const fs_builder &bld, nir_intrinsic_instr *instr,
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const fs_reg &dest, fs_reg urb_handle)
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{
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assert(instr->def.bit_size == 32);
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unsigned comps = instr->def.num_components;
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if (comps == 0)
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return;
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nir_src *offset_nir_src = nir_get_io_offset_src(instr);
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assert(nir_src_is_const(*offset_nir_src));
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fs_builder ubld16 = bld.group(16, 0).exec_all();
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const unsigned offset_in_dwords = nir_intrinsic_base(instr) +
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nir_src_as_uint(*offset_nir_src) +
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component_from_intrinsic(instr);
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if (offset_in_dwords > 0) {
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fs_reg new_handle = ubld16.vgrf(BRW_REGISTER_TYPE_UD);
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ubld16.ADD(new_handle, urb_handle, brw_imm_ud(offset_in_dwords * 4));
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urb_handle = new_handle;
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}
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fs_reg data = ubld16.vgrf(BRW_REGISTER_TYPE_UD, comps);
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fs_reg srcs[URB_LOGICAL_NUM_SRCS];
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srcs[URB_LOGICAL_SRC_HANDLE] = urb_handle;
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fs_inst *inst = ubld16.emit(SHADER_OPCODE_URB_READ_LOGICAL,
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data, srcs, ARRAY_SIZE(srcs));
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inst->size_written = 2 * comps * REG_SIZE;
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for (unsigned c = 0; c < comps; c++) {
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fs_reg dest_comp = offset(dest, bld, c);
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fs_reg data_comp = horiz_stride(offset(data, ubld16, c), 0);
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bld.MOV(retype(dest_comp, BRW_REGISTER_TYPE_UD), data_comp);
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}
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}
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static void
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emit_urb_indirect_reads(const fs_builder &bld, nir_intrinsic_instr *instr,
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const fs_reg &dest, const fs_reg &offset_src, fs_reg urb_handle)
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@ -1936,6 +2089,53 @@ emit_urb_indirect_reads(const fs_builder &bld, nir_intrinsic_instr *instr,
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}
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}
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static void
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emit_urb_indirect_reads_xe2(const fs_builder &bld, nir_intrinsic_instr *instr,
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const fs_reg &dest, const fs_reg &offset_src,
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fs_reg urb_handle)
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{
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assert(instr->def.bit_size == 32);
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unsigned comps = instr->def.num_components;
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if (comps == 0)
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return;
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fs_builder ubld16 = bld.group(16, 0).exec_all();
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const unsigned offset_in_dwords = nir_intrinsic_base(instr) +
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component_from_intrinsic(instr);
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if (offset_in_dwords > 0) {
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fs_reg new_handle = ubld16.vgrf(BRW_REGISTER_TYPE_UD);
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ubld16.ADD(new_handle, urb_handle, brw_imm_ud(offset_in_dwords * 4));
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urb_handle = new_handle;
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}
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fs_reg data = ubld16.vgrf(BRW_REGISTER_TYPE_UD, comps);
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for (unsigned q = 0; q < bld.dispatch_width() / 16; q++) {
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fs_builder wbld = bld.group(16, q);
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fs_reg addr = wbld.vgrf(BRW_REGISTER_TYPE_UD);
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wbld.SHL(addr, horiz_offset(offset_src, 16 * q), brw_imm_ud(2));
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wbld.ADD(addr, addr, urb_handle);
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fs_reg srcs[URB_LOGICAL_NUM_SRCS];
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srcs[URB_LOGICAL_SRC_HANDLE] = addr;
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fs_inst *inst = wbld.emit(SHADER_OPCODE_URB_READ_LOGICAL,
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data, srcs, ARRAY_SIZE(srcs));
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inst->size_written = 2 * comps * REG_SIZE;
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for (unsigned c = 0; c < comps; c++) {
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fs_reg dest_comp = horiz_offset(offset(dest, bld, c), 16 * q);
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fs_reg data_comp = offset(data, wbld, c);
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wbld.MOV(retype(dest_comp, BRW_REGISTER_TYPE_UD), data_comp);
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}
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}
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}
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void
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fs_visitor::emit_task_mesh_store(const fs_builder &bld, nir_intrinsic_instr *instr,
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const fs_reg &urb_handle)
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@ -1944,8 +2144,15 @@ fs_visitor::emit_task_mesh_store(const fs_builder &bld, nir_intrinsic_instr *ins
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nir_src *offset_nir_src = nir_get_io_offset_src(instr);
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if (nir_src_is_const(*offset_nir_src)) {
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emit_urb_direct_writes(bld, instr, src, urb_handle);
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if (bld.shader->devinfo->ver >= 20)
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emit_urb_direct_writes_xe2(bld, instr, src, urb_handle);
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else
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emit_urb_direct_writes(bld, instr, src, urb_handle);
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} else {
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if (bld.shader->devinfo->ver >= 20) {
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emit_urb_indirect_writes_xe2(bld, instr, src, get_nir_src(*offset_nir_src), urb_handle);
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return;
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}
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bool use_mod = false;
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unsigned mod;
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@ -1978,10 +2185,17 @@ fs_visitor::emit_task_mesh_load(const fs_builder &bld, nir_intrinsic_instr *inst
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* a single large aligned read instead one per component.
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*/
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if (nir_src_is_const(*offset_nir_src))
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emit_urb_direct_reads(bld, instr, dest, urb_handle);
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else
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emit_urb_indirect_reads(bld, instr, dest, get_nir_src(*offset_nir_src), urb_handle);
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if (nir_src_is_const(*offset_nir_src)) {
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if (bld.shader->devinfo->ver >= 20)
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emit_urb_direct_reads_xe2(bld, instr, dest, urb_handle);
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else
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emit_urb_direct_reads(bld, instr, dest, urb_handle);
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} else {
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if (bld.shader->devinfo->ver >= 20)
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emit_urb_indirect_reads_xe2(bld, instr, dest, get_nir_src(*offset_nir_src), urb_handle);
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else
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emit_urb_indirect_reads(bld, instr, dest, get_nir_src(*offset_nir_src), urb_handle);
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}
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}
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void
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