The ISL_AUX_USAGE_STC_CCS is the last defined usage. We could
get a random value from isl_encode_aux_mode[] once it is passed
as index if its element is not initialized.
Explicit initialization of ISL_AUX_USAGE_HIZ_CCS_WT is added too.
Suggested by Nanley Chery <nanley.g.chery@intel.com>
Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29906>
The render surface state doesn't have these features any
more since Xe2.
Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29906>
Update mapping between render target surface formats and
compression formats.
Some preexisting correct mappings are also re-ordered to
the order of types in the spec for an easier verification
(top to bottom and left to right).
Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29905>
Pass struct isl_tile_info to isl_choose_image_alignment_el() and its
subfunctions. We already compute isl_tile_info at isl_surf_init_s(),
don't make the subfunctions compute it again, just reuse the results.
Other subfunctions of isl_surf_init_s() also take the tile info as an
argument instead of recomputing it.
v2: Rebase after the gen20 version was added.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> (v1)
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com> (v2)
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29337>
I got the image alignment requirements for CPCB surfaces from Bspec
authors. The vertical alignment value of 8 was confirmed through the
Vulkan CTS test group, dEQP-VK.fragment_shading_rate*layered*. It also
happens to match the QPitch alignment requirement documented in the
Bspec. Hopefully the CTS will add tests for LOD2+ in order to exercise
the horizontal alignment value.
With this in place, we can start using Tile4.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10784
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29355>
Some applications may benefit from this while some can get a performance
hit. Default to false and make it possible to toggle only for selected
workloads.
See workaround 14022483228 for some measurements.
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29760>
This will disable cases with 2D array views (which could be views to 3D
texture) but enables on regular 2D surfaces which seems to work fine.
Fixes: 70382f7f06 ("intel/isl/xe2: Enable route of Sampler LD message to LSC")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29760>
The new Xe2 files are copyed from intel/isl/isl_gfx12.*, as the
base for a seperation.
From 59218cdf07.
Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29702>
On gfx12.0, CCS fast clears don't seem to cover the correct portion of
the aux buffer when the pitch is not 512B-aligned. Pad the pitch unless
Wa_18020603990 applies (slow clear surfaces up to 256x256, 32bpp).
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29659>
Filter out X-tiling early to avoid an assert failure in the next patch.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29659>
Intel modifiers supporting compression are specified to be compatible
with the display engine, even if they won't actually be used for
scanout.
Attempting to capture a wider scope of modifiers resulted in test
errors. I chose to narrow the scope instead of digging into them.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29659>
Now that we're using macros to handle aux-map CCS layout, we have no
need for the ISL surface representation.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29659>
This workaround ask us to set a dummy aux address to all
SURFTYPE_BUFFERs with AuxiliarySurfaceMode == AUX_NONE.
It also says that the same dummy aux address can be reused acrsoss all
buffers.
So here adding dummy_aux_address to isl_device, ANV and Iris will
set a value to when running a in a GPU affected.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29619>
The restriction on depth aux mode is gone on Xe2 in spec.
Fix: piglit
arb_post_depth_coverage-multisampling -auto -fbo
isl_surface_state.c:723: isl_gfx20_surf_fill_state_s:
Assertion `info->surf->samples == 1' failed.
Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29274>
In the import paths in iris, there are several cases where surface VMAs
are created without relying on the calculated surface alignment.
Asserting the alignments of surface addresses, should help catch any
cases where we end up with the wrong alignment.
This found a couple issues during development. One which required a
change to existing code is that when creating uncompressed surfaces from
compressed ones, ISL will sometimes increase the image alignment as a
result of the new format supporting CCS. This patch adds the usage flag
to disable that behavior.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29094>
Add and use two new surf usage bits:
* ISL_SURF_USAGE_MULTI_ENGINE_SEQ_BIT: the surface may be accessed by
multiple engines, but not in parallel.
* ISL_SURF_USAGE_MULTI_ENGINE_PAR_BIT: the surface may be accessed by
multiple engines in parallel.
Both usages are not concerned with read-after-read access patterns.
Using these bits allows ISL to conditionally use Tile64 or a 64KB
alignment to account for the gfx12.5 CCS WA from HSD 22015614752. Apart
from the potential space savings, there are three benefits of this
approach:
1) CCS can now be used with miptails (though nothing makes use of this
today).
2) CCS can now be used with 3D depth/stencil surfaces in GL.
3) CCS can now be used with 3D depth/stencil surfaces in Vulkan when
apps only use a single queue.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11111
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11117
Tested-by: Mark Janes <markjanes@swizzler.org>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29094>
In iris, use the CCS scale down factor to calculate the impact of CCS on
TBIMR tile sizes. Even though we fall back to a seemingly less accurate
method to calculate the impact of CCS, it ends up giving the same
answer, 1bpp. Anv already uses this factor, so this patch replaces the
constant with this macro.
There are two benefits to doing this:
1) Consistency between anv and iris.
2) Preparation for a future where we no longer use ISL surfaces to
describe CCS on Xe+. In fact, in iris, we already don't create such
surfaces on ACM.
I considered using INTEL_AUX_MAP_MAIN_SIZE_SCALEDOWN for the calculation
in both drivers, but the naming is aux-map specific and the scaledown
actually exists on flat-ccs platforms as well.
So, we introduce a new macro for all Xe platforms, currently only used
for the specific use case of TBIMR calculations. We can add more such
macros for future platforms, as needed.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28942>
At the interfaces which query the pitch of the clear color plane in GL
and Vulkan, we've been returning 64B for various reasons. Unify the
rationale under a macro.
The documentation for the macro is picked from anv, which reflects the
most recently synchronized copy of drm_fourcc.h. See the notable changes
at 8cd8f3d697.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28942>
The only remaining restriction applies to single sampled 3D textures on
Gen12.0. Move the check to disable CCS on such resources to the right
place.
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28646>
We were accidentally leaving XY_BLOCK_COPY_BLT's Source and Destination
MOCS fields set to 0 (Error: Reserved for Non-Use) on Gfx12.0 systems.
This was causing assert fails in debug builds, since we try to ensure
that we don't do that. In theory, MOCS 0 is supposed to be equivalent
to MOCS 2 (all the caching), but...we probably ought to use MOCS 3
(uncached). Every Gfx12.5+ platform requires it, so although there
isn't a note about Gfx12.0 needing that, it's possible that it does.
We're currently only using the blitter for DRI PRIME blits on Gfx12.0,
anyway, and I think we're flushing all the caches regardless.
This bug was somewhat obscure to hit:
- You need a hybrid graphics system with Gfx12.0 and some other GPU
- You have to be using "reverse PRIME", i.e. rendering on the integrated
GPU and displaying on the discrete one. This is not the common case.
- You have to be using a debug build.
No observable performance delta in GfxBench5 Car Chase (an arbitrary
program) when rendering on Alderlake GT1 and displaying on an Arc A770.
Fixes: 194afe8416 ("anv/iris/blorp: use the right MOCS values for each engine")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28894>
Bspec 57023: RENDER_SURFACE_STATE::Shader Channel Select Red
"For channels not present in the surface format, the corresponding
Surface Channel Select is either SCS_ZERO or SCS_ONE."
This restriction applies to alpha channel as well if an associated
resource is not used as a render target.
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28791>
Bspec 57023: RENDER_SURFACE_STATE:: Shader Channel Select Red
"Render Target messages do not support swapping of colors with
alpha. The Red, Green, or Blue Shader Channel Selects do not
support SCS_ALPHA. The Shader Channel Select Alpha does not support
SCS_RED, SCS_GREEN, or SCS_BLUE."
Cc: mesa-stable
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28791>
For HSD 22015614752, we enabled Tile64 to ensure image subresources are
64K aligned. However, we neglected to disable miptails so some image
miplevels actually did not achieve the desired image alignment. Do that
now.
Fixes: c6686fda28 ("intel/isl: Use Tile64 to align images for CCS WA")
Reported-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28703>
Not setting this bits, it seems we get incorrect depth values (i.e
not zero) for null depth/stencil tiles.
Fixes vkd3d-proton's test_sparse_depth_stencil_rendering
CTS doesn´t seem to exercise any depth/stencil format.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28611>
See HSD 22015614752. We have issues when multiple engines access the
same CCS cacheline in parallel. This can happen in a Vulkan application
that uses different queues to operate on different subresources.
To resolve this, this patch prefers Tile64 when an image has multiple
subresources and disallows CCS if such an image lacks that tiling.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8614
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28284>
WA 22015614752 applies to gfx125 platforms, but the alignment
requirement was only enabled for the subset that has an aux-map. Adjust
the condition to apply it where appropriate.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28284>
We guard surface state encoding of tilings by macros when the encoded
value is not present on certain platforms. For gfx20 however, we added
these macros even when the existing ones for gfx125 were sufficient.
Remove the extra macros.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28284>
We don't check the gfx version when choosing the tiling except when
choosing Tile64. Drop the version check for consistency and to remove
doubts about the order of operations occuring as expected within the
CHOOSE macro.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28284>
