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isl: Update isl_gfx20 code (xe2)
Purge code for previous platforms and rename functions in Xe2 files. Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com> Reviewed-by: Rohan Garg <rohan.garg@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29702>
This commit is contained in:
Jianxun Zhang
Marge Bot
parent
67fb44ccd6
commit
5de9df094f
2 changed files with 30 additions and 111 deletions
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2018 Intel Corporation
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* Copyright (c) 2024 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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@ -21,8 +21,7 @@
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* IN THE SOFTWARE.
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*/
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#include "isl_gfx9.h"
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#include "isl_gfx12.h"
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#include "isl_gfx20.h"
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#include "isl_priv.h"
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/**
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@ -37,23 +36,20 @@
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* flags except ISL_TILING_4_BIT, ISL_TILING_X_BIT, and ISL_TILING_LINEAR_BIT.
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*/
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void
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isl_gfx125_filter_tiling(const struct isl_device *dev,
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const struct isl_surf_init_info *restrict info,
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isl_tiling_flags_t *flags)
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isl_gfx20_filter_tiling(const struct isl_device *dev,
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const struct isl_surf_init_info *restrict info,
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isl_tiling_flags_t *flags)
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{
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/* Clear flags unsupported on this hardware */
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assert(ISL_GFX_VERX10(dev) >= 125);
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const isl_tiling_flags_t tile64_bit =
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ISL_GFX_VERX10(dev) >= 200 ? ISL_TILING_64_XE2_BIT : ISL_TILING_64_BIT;
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assert(ISL_GFX_VERX10(dev) >= 200);
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*flags &= ISL_TILING_LINEAR_BIT |
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ISL_TILING_X_BIT |
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ISL_TILING_4_BIT |
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tile64_bit;
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ISL_TILING_64_XE2_BIT;
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if (isl_surf_usage_is_depth_or_stencil(info->usage)) {
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*flags &= ISL_TILING_4_BIT | ISL_TILING_STD_64_MASK;
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*flags &= ISL_TILING_4_BIT | ISL_TILING_64_XE2_BIT;
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/* We choose to avoid Tile64 for 3D depth/stencil buffers. The swizzle
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* for Tile64 is dependent on the image dimension. So, reads and writes
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@ -64,11 +60,11 @@ isl_gfx125_filter_tiling(const struct isl_device *dev,
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* 3DSTATE_(DEPTH|STENCIL)_BUFFER.
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*/
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if (info->dim == ISL_SURF_DIM_3D)
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*flags &= ~ISL_TILING_STD_64_MASK;
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*flags &= ~ISL_TILING_64_XE2_BIT;
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}
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if (info->usage & ISL_SURF_USAGE_DISPLAY_BIT)
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*flags &= ~ISL_TILING_STD_64_MASK;
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*flags &= ~ISL_TILING_64_XE2_BIT;
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/* From RENDER_SURFACE_STATE::AuxiliarySurfaceMode,
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*
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@ -105,13 +101,13 @@ isl_gfx125_filter_tiling(const struct isl_device *dev,
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* will not support as Tile64"
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*/
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if (isl_format_is_yuv(info->format))
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*flags &= ~ISL_TILING_STD_64_MASK;
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*flags &= ~ISL_TILING_64_XE2_BIT;
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/* Tile64 tilings for 3D have a different swizzling than a 2D surface. So
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* filter them out if the usage wants 2D/3D compatibility.
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*/
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if (info->usage & ISL_SURF_USAGE_2D_3D_COMPATIBLE_BIT)
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*flags &= ~ISL_TILING_STD_64_MASK;
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*flags &= ~ISL_TILING_64_XE2_BIT;
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/* From RENDER_SURFACE_STATE::NumberofMultisamples,
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*
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@ -122,11 +118,11 @@ isl_gfx125_filter_tiling(const struct isl_device *dev,
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* Tile64 is required for multisampling.
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*/
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if (info->samples > 1)
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*flags &= ISL_TILING_STD_64_MASK;
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*flags &= ISL_TILING_64_XE2_BIT;
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/* Tile64 is not defined for format sizes that are 24, 48, and 96 bpb. */
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if (isl_format_get_layout(info->format)->bpb % 3 == 0)
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*flags &= ~ISL_TILING_STD_64_MASK;
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*flags &= ~ISL_TILING_64_XE2_BIT;
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/* BSpec 46962: 3DSTATE_CPSIZE_CONTROL_BUFFER::Tiled Mode : TILE4 & TILE64
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* are the only 2 valid values.
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@ -135,23 +131,23 @@ isl_gfx125_filter_tiling(const struct isl_device *dev,
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* additional requirements for TILE4.
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*/
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if (info->usage & ISL_SURF_USAGE_CPB_BIT)
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*flags &= ISL_TILING_STD_64_MASK;
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*flags &= ISL_TILING_64_XE2_BIT;
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}
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void
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isl_gfx125_choose_image_alignment_el(const struct isl_device *dev,
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const struct isl_surf_init_info *restrict info,
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enum isl_tiling tiling,
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enum isl_dim_layout dim_layout,
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enum isl_msaa_layout msaa_layout,
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struct isl_extent3d *image_align_el)
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isl_gfx20_choose_image_alignment_el(const struct isl_device *dev,
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const struct isl_surf_init_info *restrict info,
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enum isl_tiling tiling,
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enum isl_dim_layout dim_layout,
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enum isl_msaa_layout msaa_layout,
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struct isl_extent3d *image_align_el)
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{
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/* Handled by isl_choose_image_alignment_el */
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assert(info->format != ISL_FORMAT_GFX125_HIZ);
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const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
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if (isl_tiling_is_64(tiling)) {
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if (tiling == ISL_TILING_64_XE2) {
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/* From RENDER_SURFACE_STATE::SurfaceHorizontalAlignment,
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*
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* This field is ignored for Tile64 surface formats because horizontal
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@ -250,71 +246,3 @@ isl_gfx125_choose_image_alignment_el(const struct isl_device *dev,
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*image_align_el = isl_extent3d(32 * 8 / fmtl->bpb, 4, 1);
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}
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}
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void
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isl_gfx12_choose_image_alignment_el(const struct isl_device *dev,
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const struct isl_surf_init_info *restrict info,
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enum isl_tiling tiling,
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enum isl_dim_layout dim_layout,
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enum isl_msaa_layout msaa_layout,
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struct isl_extent3d *image_align_el)
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{
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/* Handled by isl_choose_image_alignment_el */
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assert(info->format != ISL_FORMAT_HIZ);
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const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
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if (fmtl->txc == ISL_TXC_CCS) {
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/* This CCS compresses a 2D-view of the entire surface. */
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assert(info->levels == 1 && info->array_len == 1 && info->depth == 1);
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*image_align_el = isl_extent3d(1, 1, 1);
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return;
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}
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if (isl_tiling_is_std_y(tiling)) {
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/* From RENDER_SURFACE_STATE::SurfaceHorizontalAlignment,
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*
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* This field is ignored for Tile64 surface formats because horizontal
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* alignment is always to the start of the next tile in that case.
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*
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* From RENDER_SURFACE_STATE::SurfaceQPitch,
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*
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* Because MSAA is only supported for Tile64, QPitch must also be
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* programmed to an aligned tile boundary for MSAA surfaces.
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*
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* Images in this surface must be tile-aligned. The table on the Bspec
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* page, "2D/CUBE Alignment Requirement", shows that the vertical
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* alignment is also a tile height for non-MSAA as well.
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*/
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struct isl_tile_info tile_info;
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isl_tiling_get_info(tiling, info->dim, msaa_layout, fmtl->bpb,
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info->samples, &tile_info);
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*image_align_el = isl_extent3d(tile_info.logical_extent_el.w,
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tile_info.logical_extent_el.h,
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1);
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} else if (isl_surf_usage_is_depth(info->usage)) {
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/* The alignment parameters for depth buffers are summarized in the
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* following table:
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*
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* Surface Format | MSAA | Align Width | Align Height
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* -----------------+-------------+-------------+--------------
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* D16_UNORM | 1x, 4x, 16x | 8 | 8
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* ----------------+-------------+-------------+--------------
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* D16_UNORM | 2x, 8x | 16 | 4
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* ----------------+-------------+-------------+--------------
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* other | any | 8 | 4
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* -----------------+-------------+-------------+--------------
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*/
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assert(isl_is_pow2(info->samples));
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*image_align_el =
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info->format != ISL_FORMAT_R16_UNORM ?
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isl_extent3d(8, 4, 1) :
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(info->samples == 2 || info->samples == 8 ?
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isl_extent3d(16, 4, 1) : isl_extent3d(8, 8, 1));
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} else if (isl_surf_usage_is_stencil(info->usage)) {
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*image_align_el = isl_extent3d(16, 8, 1);
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} else {
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isl_gfx9_choose_image_alignment_el(dev, info, tiling, dim_layout,
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msaa_layout, image_align_el);
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}
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}
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2018 Intel Corporation
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* Copyright (c) 2024 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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@ -21,8 +21,8 @@
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* IN THE SOFTWARE.
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*/
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#ifndef ISL_GFX12_H
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#define ISL_GFX12_H
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#ifndef ISL_GFX20_H
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#define ISL_GFX20_H
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#include "isl.h"
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@ -31,28 +31,19 @@ extern "C" {
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#endif
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void
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isl_gfx125_filter_tiling(const struct isl_device *dev,
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const struct isl_surf_init_info *restrict info,
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isl_tiling_flags_t *flags);
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isl_gfx20_filter_tiling(const struct isl_device *dev,
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const struct isl_surf_init_info *restrict info,
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isl_tiling_flags_t *flags);
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void
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isl_gfx125_choose_image_alignment_el(const struct isl_device *dev,
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const struct isl_surf_init_info *restrict info,
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enum isl_tiling tiling,
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enum isl_dim_layout dim_layout,
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enum isl_msaa_layout msaa_layout,
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struct isl_extent3d *image_align_el);
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void
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isl_gfx12_choose_image_alignment_el(const struct isl_device *dev,
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isl_gfx20_choose_image_alignment_el(const struct isl_device *dev,
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const struct isl_surf_init_info *restrict info,
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enum isl_tiling tiling,
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enum isl_dim_layout dim_layout,
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enum isl_msaa_layout msaa_layout,
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struct isl_extent3d *image_align_el);
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#ifdef __cplusplus
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}
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#endif
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#endif /* ISL_GFX12_H */
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#endif /* ISL_GFX20_H */
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