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intel/isl: Use Tile64 to align images for CCS WA

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See HSD 22015614752. We have issues when multiple engines access the
same CCS cacheline in parallel. This can happen in a Vulkan application
that uses different queues to operate on different subresources.

To resolve this, this patch prefers Tile64 when an image has multiple
subresources and disallows CCS if such an image lacks that tiling.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8614
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28284>
This commit is contained in:
Nanley Chery 2023-03-06 13:38:28 -08:00 • committed by Marge Bot
parent b092124186
commit c6686fda28
1 changed files with 29 additions and 0 deletions
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29
src/intel/isl/isl.c
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@ -1110,6 +1110,21 @@ isl_surf_choose_tiling(const struct isl_device *dev,
CHOOSE(ISL_TILING_LINEAR);
}
if (intel_needs_workaround(dev->info, 22015614752) &&
isl_format_supports_ccs_e(dev->info, info->format) &&
!INTEL_DEBUG(DEBUG_NO_CCS) &&
!(info->usage & ISL_SURF_USAGE_DISABLE_AUX_BIT) &&
(info->levels > 1 || info->depth > 1 || info->array_len > 1)) {
/* There are issues with multiple engines accessing the same CCS
* cacheline in parallel. This can happen if this image has multiple
* subresources. If possible, avoid such conflicts by picking a tiling
* that will increase the subresource alignment to 64k. If we can't use
* such a tiling, we'll prevent CCS from being enabled later on via
* isl_surf_supports_ccs.
*/
CHOOSE(ISL_TILING_64);
}
/* For sparse images, prefer the formats that use the standard block
* shapes.
*/
@ -3107,6 +3122,20 @@ isl_surf_supports_ccs(const struct isl_device *dev,
if (surf->row_pitch_B % 512 != 0)
return false;
if (intel_needs_workaround(dev->info, 22015614752) &&
(surf->levels > 1 ||
surf->logical_level0_px.depth > 1 ||
surf->logical_level0_px.array_len > 1)) {
/* There are issues with multiple engines accessing the same CCS
* cacheline in parallel. This can happen if this image has multiple
* subresources. Such conflicts can be avoided with tilings that set
* the subresource alignment to 64K. If we aren't using such a
* tiling, disable CCS.
*/
if (surf->tiling != ISL_TILING_64)
return false;
}
/* BSpec 44930: (Gfx12, Gfx12.5)
*
* "Compression of 3D Ys surfaces with 64 or 128 bpp is not supported