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anv/iris/blorp: use the right MOCS values for each engine

Browse source 
There are multiple problems currently :

   - blorp blitter commands overwrite the protection value coming from
     the driver
   - anv & iris are using render target MOCS for compute commands

Driver already have the ability to pass the MOCS values so we choose
to stick to that in this change. But now the driver need to select the
right MOCS depending on the engine the commands are going to run onto.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27956>
This commit is contained in:
Lionel Landwerlin 2023-12-06 12:10:09 +02:00 • committed by Marge Bot
parent c40f14bb31
commit 194afe8416
10 changed files with 124 additions and 66 deletions
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22
src/gallium/drivers/iris/iris_blit.c
View file

@ -230,13 +230,14 @@ apply_blit_scissor(const struct pipe_scissor_state *scissor,
}
void
iris_blorp_surf_for_resource(struct isl_device *isl_dev,
iris_blorp_surf_for_resource(struct iris_batch *batch,
struct blorp_surf *surf,
struct pipe_resource *p_res,
enum isl_aux_usage aux_usage,
unsigned level,
bool is_dest)
{
const struct isl_device *isl_dev = &batch->screen->isl_dev;
struct iris_resource *res = (void *) p_res;
const struct intel_device_info *devinfo = isl_dev->info;
@ -247,8 +248,7 @@ iris_blorp_surf_for_resource(struct isl_device *isl_dev,
.offset = res->offset,
.reloc_flags = is_dest ? IRIS_BLORP_RELOC_FLAGS_EXEC_OBJECT_WRITE : 0,
.mocs = iris_mocs(res->bo, isl_dev,
is_dest ? ISL_SURF_USAGE_RENDER_TARGET_BIT
: ISL_SURF_USAGE_TEXTURE_BIT),
iris_blorp_batch_usage(batch, is_dest)),
.local_hint = iris_bo_likely_local(res->bo),
},
.aux_usage = aux_usage,
@ -515,10 +515,10 @@ iris_blit(struct pipe_context *ctx, const struct pipe_blit_info *info)
IRIS_DOMAIN_RENDER_WRITE);
struct blorp_surf src_surf, dst_surf;
iris_blorp_surf_for_resource(&screen->isl_dev, &src_surf,
iris_blorp_surf_for_resource(batch, &src_surf,
&src_res->base.b, src_aux_usage,
info->src.level, false);
iris_blorp_surf_for_resource(&screen->isl_dev, &dst_surf,
iris_blorp_surf_for_resource(batch, &dst_surf,
&dst_res->base.b, dst_aux_usage,
info->dst.level, true);
@ -683,14 +683,14 @@ iris_copy_region(struct blorp_context *blorp,
struct blorp_address src_addr = {
.buffer = src_res->bo, .offset = src_res->offset + src_box->x,
.mocs = iris_mocs(src_res->bo, &screen->isl_dev,
ISL_SURF_USAGE_TEXTURE_BIT),
iris_blorp_batch_usage(batch, false /* is_dest */)),
.local_hint = iris_bo_likely_local(src_res->bo),
};
struct blorp_address dst_addr = {
.buffer = dst_res->bo, .offset = dst_res->offset + dstx,
.reloc_flags = IRIS_BLORP_RELOC_FLAGS_EXEC_OBJECT_WRITE,
.mocs = iris_mocs(dst_res->bo, &screen->isl_dev,
ISL_SURF_USAGE_RENDER_TARGET_BIT),
iris_blorp_batch_usage(batch, true /* is_dest */)),
.local_hint = iris_bo_likely_local(dst_res->bo),
};
@ -716,10 +716,10 @@ iris_copy_region(struct blorp_context *blorp,
iris_emit_buffer_barrier_for(batch, dst_res->bo, write_domain);
struct blorp_surf src_surf, dst_surf;
iris_blorp_surf_for_resource(&screen->isl_dev, &src_surf,
src, src_aux_usage, src_level, false);
iris_blorp_surf_for_resource(&screen->isl_dev, &dst_surf,
dst, dst_aux_usage, dst_level, true);
iris_blorp_surf_for_resource(batch, &src_surf, src,
src_aux_usage, src_level, false);
iris_blorp_surf_for_resource(batch, &dst_surf, dst,
dst_aux_usage, dst_level, true);
for (int slice = 0; slice < src_box->depth; slice++) {
iris_batch_maybe_flush(batch, 1500);

16
src/gallium/drivers/iris/iris_clear.c
View file

@ -325,7 +325,7 @@ fast_clear_color(struct iris_context *ice,
*/
if (devinfo->ver >= 11) {
iris_emit_pipe_control_flush(batch, "fast clear: pre-flush",
PIPE_CONTROL_STATE_CACHE_INVALIDATE |
PIPE_CONTROL_STATE_CACHE_INVALIDATE |
PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
}
@ -341,8 +341,8 @@ fast_clear_color(struct iris_context *ice,
blorp_batch_init(&ice->blorp, &blorp_batch, batch, blorp_flags);
struct blorp_surf surf;
iris_blorp_surf_for_resource(&batch->screen->isl_dev, &surf,
p_res, res->aux.usage, level, true);
iris_blorp_surf_for_resource(batch, &surf, p_res, res->aux.usage,
level, true);
blorp_fast_clear(&blorp_batch, &surf, res->surf.format,
ISL_SWIZZLE_IDENTITY,
@ -411,8 +411,7 @@ clear_color(struct iris_context *ice,
iris_emit_buffer_barrier_for(batch, res->bo, IRIS_DOMAIN_RENDER_WRITE);
struct blorp_surf surf;
iris_blorp_surf_for_resource(&batch->screen->isl_dev, &surf,
p_res, aux_usage, level, true);
iris_blorp_surf_for_resource(batch, &surf, p_res, aux_usage, level, true);
iris_batch_sync_region_start(batch);
@ -630,8 +629,8 @@ clear_depth_stencil(struct iris_context *ice,
iris_resource_prepare_render(ice, z_res, z_res->surf.format, level,
box->z, box->depth, aux_usage);
iris_emit_buffer_barrier_for(batch, z_res->bo, IRIS_DOMAIN_DEPTH_WRITE);
iris_blorp_surf_for_resource(&batch->screen->isl_dev, &z_surf,
&z_res->base.b, aux_usage, level, true);
iris_blorp_surf_for_resource(batch, &z_surf, &z_res->base.b,
aux_usage, level, true);
}
uint8_t stencil_mask = clear_stencil && stencil_res ? 0xff : 0;
@ -640,8 +639,7 @@ clear_depth_stencil(struct iris_context *ice,
box->depth, stencil_res->aux.usage, false);
iris_emit_buffer_barrier_for(batch, stencil_res->bo,
IRIS_DOMAIN_DEPTH_WRITE);
iris_blorp_surf_for_resource(&batch->screen->isl_dev,
&stencil_surf, &stencil_res->base.b,
iris_blorp_surf_for_resource(batch, &stencil_surf, &stencil_res->base.b,
stencil_res->aux.usage, level, true);
}

17
src/gallium/drivers/iris/iris_context.h
View file

@ -1237,7 +1237,7 @@ void iris_fill_cs_push_const_buffer(struct iris_screen *screen,
/* iris_blit.c */
#define IRIS_BLORP_RELOC_FLAGS_EXEC_OBJECT_WRITE (1 << 2)
void iris_blorp_surf_for_resource(struct isl_device *isl_dev,
void iris_blorp_surf_for_resource(struct iris_batch *batch,
struct blorp_surf *surf,
struct pipe_resource *p_res,
enum isl_aux_usage aux_usage,
@ -1264,6 +1264,21 @@ iris_blorp_flags_for_batch(struct iris_batch *batch)
return 0;
}
static inline isl_surf_usage_flags_t
iris_blorp_batch_usage(struct iris_batch *batch, bool is_dest)
{
switch (batch->name) {
case IRIS_BATCH_RENDER:
return is_dest ? ISL_SURF_USAGE_RENDER_TARGET_BIT : ISL_SURF_USAGE_TEXTURE_BIT;
case IRIS_BATCH_COMPUTE:
return is_dest ? ISL_SURF_USAGE_STORAGE_BIT : ISL_SURF_USAGE_TEXTURE_BIT;
case IRIS_BATCH_BLITTER:
return is_dest ? ISL_SURF_USAGE_BLITTER_DST_BIT : ISL_SURF_USAGE_BLITTER_SRC_BIT;
default:
unreachable("Unhandled batch type");
}
}
/* iris_draw.c */
void iris_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info,

20
src/gallium/drivers/iris/iris_resolve.c
View file

@ -508,8 +508,8 @@ iris_resolve_color(struct iris_context *ice,
//DBG("%s to mt %p level %u layer %u\n", __func__, mt, level, layer);
struct blorp_surf surf;
iris_blorp_surf_for_resource(&batch->screen->isl_dev, &surf,
&res->base.b, res->aux.usage, level, true);
iris_blorp_surf_for_resource(batch, &surf, &res->base.b,
res->aux.usage, level, true);
iris_batch_maybe_flush(batch, 1500);
@ -576,8 +576,8 @@ iris_mcs_exec(struct iris_context *ice,
iris_batch_maybe_flush(batch, 1500);
struct blorp_surf surf;
iris_blorp_surf_for_resource(&batch->screen->isl_dev, &surf,
&res->base.b, res->aux.usage, 0, true);
iris_blorp_surf_for_resource(batch, &surf, &res->base.b,
res->aux.usage, 0, true);
/* MCS partial resolve will read from the MCS surface. */
assert(res->aux.bo == res->bo);
@ -596,10 +596,10 @@ iris_mcs_exec(struct iris_context *ice,
* the full resolve.
*/
struct blorp_surf src_surf, dst_surf;
iris_blorp_surf_for_resource(&batch->screen->isl_dev, &src_surf,
&res->base.b, res->aux.usage, 0, false);
iris_blorp_surf_for_resource(&batch->screen->isl_dev, &dst_surf,
&res->base.b, ISL_AUX_USAGE_NONE, 0, true);
iris_blorp_surf_for_resource(batch, &src_surf, &res->base.b,
res->aux.usage, 0, false);
iris_blorp_surf_for_resource(batch, &dst_surf, &res->base.b,
ISL_AUX_USAGE_NONE, 0, true);
blorp_copy(&blorp_batch, &src_surf, 0, 0, &dst_surf, 0, 0,
0, 0, 0, 0, surf.surf->logical_level0_px.width,
@ -730,8 +730,8 @@ iris_hiz_exec(struct iris_context *ice,
iris_batch_sync_region_start(batch);
struct blorp_surf surf;
iris_blorp_surf_for_resource(&batch->screen->isl_dev, &surf,
&res->base.b, res->aux.usage, level, true);
iris_blorp_surf_for_resource(batch, &surf, &res->base.b,
res->aux.usage, level, true);
struct blorp_batch blorp_batch;
enum blorp_batch_flags flags = 0;

4
src/gallium/drivers/iris/iris_state.c
View file

@ -6089,7 +6089,9 @@ batch_emit_fast_color_dummy_blit(struct iris_batch *batch)
#if GFX_VERx10 >= 125
iris_emit_cmd(batch, GENX(XY_FAST_COLOR_BLT), blt) {
blt.DestinationBaseAddress = batch->screen->workaround_address;
blt.DestinationMOCS = batch->screen->isl_dev.mocs.blitter_dst;
blt.DestinationMOCS = iris_mocs(batch->screen->workaround_address.bo,
&batch->screen->isl_dev,
ISL_SURF_USAGE_BLITTER_DST_BIT);
blt.DestinationPitch = 63;
blt.DestinationX2 = 1;
blt.DestinationY2 = 4;

11
src/intel/blorp/blorp.h
View file

@ -132,6 +132,17 @@ void blorp_batch_init(struct blorp_context *blorp, struct blorp_batch *batch,
void *driver_batch, enum blorp_batch_flags flags);
void blorp_batch_finish(struct blorp_batch *batch);
static inline isl_surf_usage_flags_t
blorp_batch_isl_copy_usage(const struct blorp_batch *batch, bool is_dest)
{
if (batch->flags & BLORP_BATCH_USE_COMPUTE)
return is_dest ? ISL_SURF_USAGE_STORAGE_BIT : ISL_SURF_USAGE_TEXTURE_BIT;
else if (batch->flags & BLORP_BATCH_USE_BLITTER)
return is_dest ? ISL_SURF_USAGE_BLITTER_DST_BIT : ISL_SURF_USAGE_BLITTER_SRC_BIT;
else
return is_dest ? ISL_SURF_USAGE_RENDER_TARGET_BIT : ISL_SURF_USAGE_TEXTURE_BIT;
}
struct blorp_address {
void *buffer;
int64_t offset;

7
src/intel/blorp/blorp_genX_exec_brw.h
View file

@ -1998,10 +1998,6 @@ blorp_xy_block_copy_blt(struct blorp_batch *batch,
blt.SourceClearValueEnable = !!params->src.clear_color_addr.buffer;
blt.SourceClearAddress = params->src.clear_color_addr;
}
/* XeHP needs special MOCS values for the blitter */
blt.DestinationMOCS = isl_dev->mocs.blitter_dst;
blt.SourceMOCS = isl_dev->mocs.blitter_src;
#endif
}
#endif
@ -2084,8 +2080,7 @@ blorp_xy_fast_color_blit(struct blorp_batch *batch,
blt.DestinationClearAddress = params->dst.clear_color_addr;
}
/* XeHP needs special MOCS values for the blitter */
blt.DestinationMOCS = isl_dev->mocs.blitter_dst;
blt.DestinationMOCS = params->dst.addr.mocs;
#endif
}
#endif

8
src/intel/isl/isl.c
View file

@ -267,6 +267,12 @@ isl_mocs(const struct isl_device *dev, isl_surf_usage_flags_t usage,
uint32_t mask = (usage & ISL_SURF_USAGE_PROTECTED_BIT) ?
dev->mocs.protected_mask : 0;
if (usage & ISL_SURF_USAGE_BLITTER_SRC_BIT)
return dev->mocs.blitter_src | mask;
if (usage & ISL_SURF_USAGE_BLITTER_DST_BIT)
return dev->mocs.blitter_dst | mask;
if (external)
return dev->mocs.external | mask;
@ -279,7 +285,7 @@ isl_mocs(const struct isl_device *dev, isl_surf_usage_flags_t usage,
return dev->mocs.internal | mask;
if (usage & ISL_SURF_USAGE_CPB_BIT)
return dev->mocs.internal;
return dev->mocs.internal | mask;
/* Using L1:HDC for storage buffers breaks Vulkan memory model
* tests that use shader atomics. This isn't likely to work out,

2
src/intel/isl/isl.h
View file

@ -1150,6 +1150,8 @@ typedef uint64_t isl_surf_usage_flags_t;
#define ISL_SURF_USAGE_2D_3D_COMPATIBLE_BIT (1u << 19)
#define ISL_SURF_USAGE_SPARSE_BIT (1u << 20)
#define ISL_SURF_USAGE_NO_AUX_TT_ALIGNMENT_BIT (1u << 21)
#define ISL_SURF_USAGE_BLITTER_DST_BIT (1u << 22)
#define ISL_SURF_USAGE_BLITTER_SRC_BIT (1u << 23)
/** @} */
/**

83
src/intel/vulkan/anv_blorp.c
View file

@ -139,8 +139,34 @@ anv_blorp_batch_finish(struct blorp_batch *batch)
blorp_batch_finish(batch);
}
static isl_surf_usage_flags_t
get_usage_flag_for_cmd_buffer(const struct anv_cmd_buffer *cmd_buffer,
bool is_dest)
{
isl_surf_usage_flags_t usage;
switch (cmd_buffer->queue_family->engine_class) {
case INTEL_ENGINE_CLASS_RENDER:
usage = is_dest ? ISL_SURF_USAGE_RENDER_TARGET_BIT :
ISL_SURF_USAGE_TEXTURE_BIT;
break;
case INTEL_ENGINE_CLASS_COMPUTE:
usage = is_dest ? ISL_SURF_USAGE_STORAGE_BIT :
ISL_SURF_USAGE_TEXTURE_BIT;
break;
case INTEL_ENGINE_CLASS_COPY:
usage = is_dest ? ISL_SURF_USAGE_BLITTER_DST_BIT :
ISL_SURF_USAGE_BLITTER_SRC_BIT;
break;
default:
unreachable("Unhandled engine class");
}
return usage;
}
static void
get_blorp_surf_for_anv_address(struct anv_device *device,
get_blorp_surf_for_anv_address(struct anv_cmd_buffer *cmd_buffer,
struct anv_address address,
uint32_t width, uint32_t height,
uint32_t row_pitch, enum isl_format format,
@ -149,19 +175,19 @@ get_blorp_surf_for_anv_address(struct anv_device *device,
struct isl_surf *isl_surf)
{
bool ok UNUSED;
isl_surf_usage_flags_t usage =
get_usage_flag_for_cmd_buffer(cmd_buffer, is_dest);
*blorp_surf = (struct blorp_surf) {
.surf = isl_surf,
.addr = {
.buffer = address.bo,
.offset = address.offset,
.mocs = anv_mocs(device, address.bo,
is_dest ? ISL_SURF_USAGE_RENDER_TARGET_BIT
: ISL_SURF_USAGE_TEXTURE_BIT),
.mocs = anv_mocs(cmd_buffer->device, address.bo, usage),
},
};
ok = isl_surf_init(&device->isl_dev, isl_surf,
ok = isl_surf_init(&cmd_buffer->device->isl_dev, isl_surf,
.dim = ISL_SURF_DIM_2D,
.format = format,
.width = width,
@ -171,14 +197,13 @@ get_blorp_surf_for_anv_address(struct anv_device *device,
.array_len = 1,
.samples = 1,
.row_pitch_B = row_pitch,
.usage = is_dest ? ISL_SURF_USAGE_RENDER_TARGET_BIT
: ISL_SURF_USAGE_TEXTURE_BIT,
.usage = usage,
.tiling_flags = ISL_TILING_LINEAR_BIT);
assert(ok);
}
static void
get_blorp_surf_for_anv_buffer(struct anv_device *device,
get_blorp_surf_for_anv_buffer(struct anv_cmd_buffer *cmd_buffer,
struct anv_buffer *buffer, uint64_t offset,
uint32_t width, uint32_t height,
uint32_t row_pitch, enum isl_format format,
@ -186,7 +211,7 @@ get_blorp_surf_for_anv_buffer(struct anv_device *device,
struct blorp_surf *blorp_surf,
struct isl_surf *isl_surf)
{
get_blorp_surf_for_anv_address(device,
get_blorp_surf_for_anv_address(cmd_buffer,
anv_address_add(buffer->address, offset),
width, height, row_pitch, format,
is_dest, blorp_surf, isl_surf);
@ -225,10 +250,9 @@ get_blorp_surf_for_anv_image(const struct anv_cmd_buffer *cmd_buffer,
cmd_buffer->queue_family->queueFlags);
}
isl_surf_usage_flags_t mocs_usage =
(usage & VK_IMAGE_USAGE_TRANSFER_DST_BIT) ?
ISL_SURF_USAGE_RENDER_TARGET_BIT : ISL_SURF_USAGE_TEXTURE_BIT;
isl_surf_usage_flags_t isl_usage =
get_usage_flag_for_cmd_buffer(cmd_buffer,
usage & VK_IMAGE_USAGE_TRANSFER_DST_BIT);
const struct anv_surface *surface = &image->planes[plane].primary_surface;
const struct anv_address address =
anv_image_address(image, &surface->memory_range);
@ -238,7 +262,7 @@ get_blorp_surf_for_anv_image(const struct anv_cmd_buffer *cmd_buffer,
.addr = {
.buffer = address.bo,
.offset = address.offset,
.mocs = anv_mocs(device, address.bo, mocs_usage),
.mocs = anv_mocs(device, address.bo, isl_usage),
},
};
@ -254,7 +278,7 @@ get_blorp_surf_for_anv_image(const struct anv_cmd_buffer *cmd_buffer,
blorp_surf->aux_addr = (struct blorp_address) {
.buffer = aux_address.bo,
.offset = aux_address.offset,
.mocs = anv_mocs(device, aux_address.bo, 0),
.mocs = anv_mocs(device, aux_address.bo, isl_usage),
};
}
@ -625,7 +649,7 @@ copy_buffer_to_image(struct anv_cmd_buffer *cmd_buffer,
isl_format_for_size(linear_fmtl->bpb / 8);
struct isl_surf buffer_isl_surf;
get_blorp_surf_for_anv_buffer(cmd_buffer->device,
get_blorp_surf_for_anv_buffer(cmd_buffer,
anv_buffer, region->bufferOffset,
buffer_extent.width, buffer_extent.height,
buffer_layout.row_stride_B, buffer_format,
@ -985,13 +1009,13 @@ copy_buffer(struct anv_device *device,
.buffer = src_buffer->address.bo,
.offset = src_buffer->address.offset + region->srcOffset,
.mocs = anv_mocs(device, src_buffer->address.bo,
ISL_SURF_USAGE_TEXTURE_BIT),
blorp_batch_isl_copy_usage(batch, false /* is_dest */)),
};
struct blorp_address dst = {
.buffer = dst_buffer->address.bo,
.offset = dst_buffer->address.offset + region->dstOffset,
.mocs = anv_mocs(device, dst_buffer->address.bo,
ISL_SURF_USAGE_RENDER_TARGET_BIT),
blorp_batch_isl_copy_usage(batch, true /* is_dest */)),
};
blorp_buffer_copy(batch, src, dst, region->size);
@ -1060,14 +1084,16 @@ void anv_CmdUpdateBuffer(
struct blorp_address src = {
.buffer = tmp_addr.bo,
.offset = tmp_addr.offset,
.mocs = isl_mocs(&cmd_buffer->device->isl_dev,
ISL_SURF_USAGE_TEXTURE_BIT, false)
.mocs = anv_mocs(cmd_buffer->device, NULL,
get_usage_flag_for_cmd_buffer(cmd_buffer,
false /* is_dest */)),
};
struct blorp_address dst = {
.buffer = dst_buffer->address.bo,
.offset = dst_buffer->address.offset + dstOffset,
.mocs = anv_mocs(cmd_buffer->device, dst_buffer->address.bo,
ISL_SURF_USAGE_RENDER_TARGET_BIT),
get_usage_flag_for_cmd_buffer(cmd_buffer,
true /* is_dest */)),
};
blorp_buffer_copy(&batch, src, dst, copy_size);
@ -1109,12 +1135,13 @@ anv_cmd_buffer_fill_area(struct anv_cmd_buffer *cmd_buffer,
const uint64_t max_fill_size = MAX_SURFACE_DIM * MAX_SURFACE_DIM * bs;
while (size >= max_fill_size) {
get_blorp_surf_for_anv_address(cmd_buffer->device,
get_blorp_surf_for_anv_address(cmd_buffer,
(struct anv_address) {
.bo = address.bo, .offset = offset,
},
MAX_SURFACE_DIM, MAX_SURFACE_DIM,
MAX_SURFACE_DIM * bs, isl_format, true,
MAX_SURFACE_DIM * bs, isl_format,
true /* is_dest */,
&surf, &isl_surf);
blorp_clear(&batch, &surf, isl_format, ISL_SWIZZLE_IDENTITY,
@ -1128,12 +1155,13 @@ anv_cmd_buffer_fill_area(struct anv_cmd_buffer *cmd_buffer,
assert(height < MAX_SURFACE_DIM);
if (height != 0) {
const uint64_t rect_fill_size = height * MAX_SURFACE_DIM * bs;
get_blorp_surf_for_anv_address(cmd_buffer->device,
get_blorp_surf_for_anv_address(cmd_buffer,
(struct anv_address) {
.bo = address.bo, .offset = offset,
},
MAX_SURFACE_DIM, height,
MAX_SURFACE_DIM * bs, isl_format, true,
MAX_SURFACE_DIM * bs, isl_format,
true /* is_dest */,
&surf, &isl_surf);
blorp_clear(&batch, &surf, isl_format, ISL_SWIZZLE_IDENTITY,
@ -1145,12 +1173,13 @@ anv_cmd_buffer_fill_area(struct anv_cmd_buffer *cmd_buffer,
if (size != 0) {
const uint32_t width = size / bs;
get_blorp_surf_for_anv_address(cmd_buffer->device,
get_blorp_surf_for_anv_address(cmd_buffer,
(struct anv_address) {
.bo = address.bo, .offset = offset,
},
width, 1,
width * bs, isl_format, true,
width * bs, isl_format,
true /* is_dest */,
&surf, &isl_surf);
blorp_clear(&batch, &surf, isl_format, ISL_SWIZZLE_IDENTITY,