Commit graph

22170 commits

Author SHA1 Message Date
Tom Stellard
8e7df519bd clover: Add support for compiling to native object code v3
v2:
  - Split build_module_native() into three separate functions.
  - Code cleanups.

v3:
  - More cleanups.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2014-10-16 19:42:30 -04:00
Tom Stellard
8b7cc90cef gallium: Add PIPE_SHADER_IR_NATIVE to enum pipe_shader_ir
Drivers can return this value for PIPE_COMPUTE_CAP_IR_TARGET
if they want clover to give them native object code.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2014-10-16 19:42:22 -04:00
Tom Stellard
dc39b32c9b clover: Factor kernel argument parsing into its own function v2
v2:
  - Code cleanups.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2014-10-16 19:42:14 -04:00
Emil Velikov
79d09a4b12 vc4: correctly include the source files
The kernel files are built into a separate static library and
all the functions that require it are already wrapped in ifdef
USE_VC4_SIMULATOR. Don't forget the header file :)

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2014-10-16 10:00:14 +01:00
Rob Clark
652b8fbbbb freedreno/ir3: large const support
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-10-15 15:49:49 -04:00
Rob Clark
e71a3f80fb freedreno: update generated headers
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-10-15 15:49:48 -04:00
Rob Clark
dd332fe641 freedreno: fix layer_stride
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-10-15 15:49:48 -04:00
Rob Clark
8233b36a17 freedreno: inline fd_draw_emit()
Manual LTO

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-10-15 15:49:48 -04:00
Rob Clark
368466b7b7 freedreno/ir3: optimize shader key comparision
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-10-15 15:49:48 -04:00
Rob Clark
d595987ea3 freedreno/a3xx: refactor/optimize emit
Because we reuse various bits of emit code (for state/vertex/prog/etc)
for both regular draws and internal draws (gmem<->mem, clear, etc), the
number of parameters getting passed around has been growing.  Refactor
to group these into fd3_emit.  This simplifies fxn signatures, avoids
passing around shader key on the stack, etc.  It also gives us a nice
place to cache shader-variant lookup to avoid looking up shader variants
multiple times per draw (without having to *also* pass them around as
fxn args everywhere).

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-10-15 15:49:48 -04:00
Rob Clark
d5d80b3739 freedreno/a3xx: refactor vertex state emit
Get rid of fd3_vertex_buf and use fd_vertex_state directly for all
draws.  Removes a tiny bit of CPU overhead for munging around the vertex
state every time it is emitted, but more importantly it cleans things up
for later optimizations, so the emit paths don't have to special case
internal draws (gmem<->mem, clears, etc) with regular draws.

Instead of constructing fd3_vertex_buf array each time for internal
draws, and context init time pre-create solid_vbuf_state and
blit_vbuf_state.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-10-15 15:49:48 -04:00
Eric Anholt
57de9bbb63 vc4: Fix the uniform debug output.
I dropped the shader index when moving to the compiled shader struct, but
didn't update the format string here.
2014-10-15 18:12:03 +01:00
Eric Anholt
201d4c0b2a vc4: Add support for user clip plane and gl_ClipVertex.
Fixes about 15 piglit tests about interpolation and clipping.
2014-10-15 18:11:46 +01:00
Eric Anholt
6a0bf67048 vc4: Move the output semantics setup to a helper.
I want to reuse it elsewhere to set up outputs that aren't in the TGSI.
2014-10-15 18:11:46 +01:00
Michel Dänzer
159f93cf39 r600g,radeonsi: Only set use_staging_texture = TRUE once
No need to check for setting the flag after we set it already.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-10-15 16:26:30 +09:00
Michel Dänzer
87da286755 r600g,radeonsi: Use staging texture for transfers if any miplevel is tiled
We set the NO_CPU_ACCESS flag for BO allocation in that case, so direct CPU
access may not work.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-10-15 16:26:14 +09:00
Michel Dänzer
3ede67a4c6 winsys/radeon: Use separate caching buffer manager for each set of flags
Otherwise the caching buffer manager may return a buffer which was created
with a different set of flags, which can cause trouble.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-10-15 16:11:40 +09:00
Tom Stellard
8cf6482c3d clover: Fix regression in module serialization
We need to serialize semantic information for arguments, which was added
in 06139c56fa.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2014-10-14 17:58:06 -04:00
Ilia Mirkin
742158b51e st/gbm: fix order of arguments passed to is_format_supported
Reported by Coverity

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Cc: mesa-stable@lists.freedesktop.org
2014-10-14 12:33:38 -04:00
Rob Clark
abe3b3d1e0 freedreno: use tgsi_lowering
Now that the freedreno_lowering code is moved to tgsi_lowering, remove
our private copy and switch over to using the common version.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-10-14 12:30:08 -04:00
David Heidelberger
d2c1d9693f r300/compiler: remove useless check
This code is already in if (!variable->C->is_r500) so no need check
twice.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: David Heidelberger <david.heidelberger@ixit.cz>
2014-10-14 12:18:32 -04:00
Nick Sarnie
e5bf8d38db ilo: Build pipe-loader for ilo
Trivial patch to create the pipe loader for ilo. All the code was already there.

Signed-off-by: Nick Sarnie <commendsarnex@gmail.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2014-10-14 16:16:08 +01:00
Emil Velikov
af897df508 automake: explicitly set TARGET_RADEON_{WINSYS,COMMON}
Originally the variables were set only once via the ?= operator but
that causes issues when doing incremental builds. They appear to be
undefined and missing from the dependency list despite their addition
to LIBADD.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=84807
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2014-10-14 16:16:08 +01:00
Eric Anholt
a2d8b6dbd5 vc4: Fix render target NPOT alignment at small miplevels.
The texturing hardware takes the POT level 0 width/height and minifies
those.  This is different from what we were doing, for example, for
273-wide's level 5: POT(273>>5) == 8, while POT(273)>>5 == 16.

Fixes piglit-depthstencil-render-miplevels 273.
2014-10-14 14:57:50 +01:00
Eric Anholt
b5fc9d5664 vc4: Add support for having 0 vertex elements used.
You have to load at least 1, according to the simulator.  Fixes 4 piglit
tests and even more ES2 conformance tests.
2014-10-14 11:29:48 +01:00
Vinson Lee
a2fd55cfb6 auxilary/os: Add DragonFly BSD support in os_get_total_physical_memory.
This patch fixes this build error on DragonFly BSD.

  CC       os/os_misc.lo
os/os_misc.c: In function 'os_get_total_physical_memory':
os/os_misc.c:132:2: error: #error Unsupported *BSD

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
2014-10-13 23:40:46 -07:00
Chia-I Wu
4e2cf84b1f ilo: clear writer pointer after unmapping
It does not look like an issue now but it is good to be future proof.  Spotted
by Courtney Goeltzenleuchter.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
2014-10-14 08:54:25 +08:00
Eric Anholt
615bbf0ca6 vc4: Write the VPM read setup multiple times to queue all the inputs.
There's a 4-element fifo, and the size (number of dwords per vertex) field
is just 4 bits.

Fixes glsl-routing on sim.
2014-10-13 17:16:05 +01:00
Eric Anholt
e1d1c39626 vc4: Add support for the TXL opcode.
There's a bit at the bottom of cube map stride (which has some formatting
bugs in the docs) which flips the bias coordinate to being an absolute
LOD.
2014-10-13 17:15:47 +01:00
Eric Anholt
5bc91b6e32 vc4: Improve the accuracy of SIN and COS.
This gets them to pass glsl-sin/cos.  There was an obvious problem that I
was using the FRC code on the scaled input value, which means that we had
a range in [0, 1], while our taylor is most accurate across [-0.5, 0.5].
We can just slide things over, but that means flipping the sign of the
coefficients.  After that, it was just a matter of stuffing more
coefficients in.
2014-10-13 17:15:47 +01:00
Eric Anholt
5d72a1c956 vc4: Match VS outputs to FS inputs.
If the VS doesn't output a value that the FS needs, we still need to read
the right contents for the remaining FS inputs, by emitting padding.  And
if the VS outputs something the FS doesn't need, we shouldn't put it in
the VPM at all (so the code producing it can get DCEed).

Fixes 77 piglit tests.
2014-10-13 13:23:48 +01:00
Eric Anholt
83365a5b57 vc4: Add support for the CEIL opcode.
Not as big of a deal as SSG, but still +9 piglit tests.
2014-10-13 08:06:48 +01:00
Eric Anholt
926eaa9af4 vc4: Add support for the SSG opcode. 2014-10-13 08:06:48 +01:00
Glenn Kennard
a327fa3a06 r600g: Implement GL_ARB_sample_shading
Also fixes two sided lighting which was broken at least
on pre-evergreen by commit b1eb00.

Signed-off-by: Glenn Kennard <glenn.kennard@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2014-10-12 23:53:57 +02:00
Marek Olšák
75e97e2e3f radeonsi: use tgsi_shader_info in si_llvm_emit_fs_epilogue
This is the last use tgsi_parse_token in radeonsi.

It looks ugly because the code was re-indented, but there is really no change
in behavior.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-10-12 23:53:57 +02:00
Marek Olšák
558f7770a7 radeonsi: remove si_shader_output_values::index
It's redundant now.

It led to a simplification in si_llvm_emit_streamout, because outidx == reg.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-10-12 23:53:57 +02:00
Marek Olšák
ec0d16872b radeonsi: use tgsi_shader_info in si_llvm_emit_vs_epilogue
That code was really ugly.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-10-12 23:53:57 +02:00
Marek Olšák
8067732740 radeonsi: remove shader->input[] and output[] arrays and dependencies
They were reinventing tgsi_shader_info. They are unused now.

radeon_llvm_context::load_input can be NULL if input fetching is implemented
in some other way.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-10-12 23:53:57 +02:00
Marek Olšák
8b057ddaea radeonsi: move param_offset out of shader->input[] and output[]
Those are going away.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-10-12 23:53:57 +02:00
Marek Olšák
02134cfaae radeonsi: use tgsi_shader_info to get a list of GS outputs
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-10-12 23:53:54 +02:00
Marek Olšák
101905d3f7 radeonsi: use tgsi_shader_info in si_update_spi_map
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-10-12 23:53:54 +02:00
Marek Olšák
6f04cf7fac radeonsi: simplify dereferences in si_update_spi_map
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-10-12 23:53:54 +02:00
Marek Olšák
639f6b41d2 radeonsi: use tgsi_shader_info in si_shader_vs
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-10-12 23:53:54 +02:00
Marek Olšák
fa933438a2 radeonsi: use tgsi_shader_info in si_shader_ps
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-10-12 23:53:54 +02:00
Marek Olšák
e23fec1445 radeonsi: use tgsi_shader_info in fetch_input_gs
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-10-12 23:53:51 +02:00
Marek Olšák
7a645c5366 radeonsi: don't rely on shader->output in si_llvm_emit_fs_epilogue
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-10-12 23:52:16 +02:00
Marek Olšák
216cf86ec4 radeonsi: use tgsi_shader_info in si_llvm_emit_es_epilogue
tgsi_shader_info contains everything we need.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-10-12 23:52:13 +02:00
Marek Olšák
34e8200599 radeonsi: don't recompile shaders when changing nr_cbufs from 0 to 1
Both cases are equivalent.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-10-12 23:52:07 +02:00
Marek Olšák
5e0fbe1b63 radeonsi: remove vs.ucps_enabled from the shader key
Written CLIPDIST outputs are simply disabled in PA_CL_VS_OUT_CNTL.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-10-12 23:52:02 +02:00
Marek Olšák
a9592cd3ac radeonsi: assume ClipDistance usage mask is always 0xf
No code in Mesa sets the usage mask to any other value.
The final mask is AND'ed with enable bits from the rasterizer state anyway.

If somebody implements setting usage masks in st/mesa, we can use
tgsi_shader_info to get it more easily.

This is a prerequisite for the following commit.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-10-12 23:51:44 +02:00