Brian
fbe68bf6b2
Simplify draw module's vertex_info.
...
No longer store the vertex header and clip pos info in the draw module's
vertex_info. The vertex_info just describes the data[] elements.
This simplifies the code in several places.
2007-11-21 15:40:20 -07:00
Ben Skeggs
dd1500b8b4
nouveau: wait for sync after m2mf also, to be thourough.
...
These will all go away at some point I promise, want to rule out sync issues
while I bash nv40 into shape.
2007-11-21 19:21:34 +11:00
Ben Skeggs
ff7edad077
nv40: Better teximage layout, probably not 100% correct still.
...
Gallium represents image layout by saying that each mipmap level has a number
of "face" images within it. However, nv40 represents them as "faces" that
have a number of mipmap levels. I'm not sure if the gallium representation
allows this, but I've made an attempt to match it as closely as possible.
CUBE/3D textures with mipmaps are probably broken, but untested currently.
2007-11-21 19:20:38 +11:00
Ben Skeggs
af1a388939
Merge branch 'upstream-gallium-0.1' into darktama-gallium-0.1
2007-11-21 15:38:28 +11:00
Eric Anholt
93c98a4669
[965] Replace 965 texture format code with common code.
...
The only functional difference should be that 965 now gets the optimization
where textures default to 16bpp when the screen is 16bpp.
2007-11-20 11:30:12 -08:00
Eric Anholt
e962997429
[965] Remove dead exec vfmt code which was replaced by generic vbo code.
2007-11-20 11:30:10 -08:00
Brian
5a6017d496
add PIPE_FORMAT_Z24_S8 support to softpipe patsh
2007-11-20 08:36:06 -07:00
Brian
0191570f02
initial support for PIPE_FORMAT_Z24_S8
2007-11-20 08:30:10 -07:00
Brian
827e72de75
clamp lambda to Min/MaxLod
2007-11-20 08:24:46 -07:00
Ben Skeggs
0655cdcf48
nv40: force reupload of all consts on vtxprog change
2007-11-20 22:34:55 +11:00
Ben Skeggs
0d0349faff
nouveau: temporary workaround for dodgy buffer code
2007-11-20 22:09:56 +11:00
Ben Skeggs
b9b5f4b3c1
nv40: "rect" textures, anisotropic filtering
2007-11-20 21:13:33 +11:00
Ben Skeggs
30837fd24f
nv40: fix a couple of typos
2007-11-20 20:56:47 +11:00
Ben Skeggs
f01e305e98
nv40: use native Z24_S8 format for zeta buffer
2007-11-20 19:10:58 +11:00
Ben Skeggs
85d626508a
Add support for Z24_S8 to GL state tracker.
2007-11-20 19:09:47 +11:00
Ben Skeggs
04fcee96b1
nv40: track pipe const id
2007-11-20 19:08:33 +11:00
Ben Skeggs
b4c813313a
nv40: remove use of temps for KILP, implement KIL
2007-11-20 15:34:26 +11:00
Ben Skeggs
060127af38
nouveau: update to latest header
2007-11-20 13:22:11 +11:00
Brian
c4f9fbb57f
optimize earlyz_quad(), add comments, remove unneeded #includes
2007-11-19 18:16:07 -07:00
Brian
0204cbb4f1
optimize linear_interpolation(), perspective_interpolation() functions
2007-11-19 18:15:21 -07:00
Eric Anholt
3821d15e06
[965] Add INTEL_DEBUG=fall debugging output.
2007-11-19 15:29:31 -08:00
Eric Anholt
27674c4135
[965] Convert DBG macro to use FILE_DEBUG_FLAG like i915.
2007-11-19 15:28:26 -08:00
Brian
87373e3072
fix some texture format assertions, etc
2007-11-19 10:37:54 -07:00
Brian
22a374fc3f
fix out-of-bounds array index (ix=-1)
2007-11-19 09:55:47 -07:00
Michal Krol
7f718f0476
Implement early depth test.
...
Early depth test is enabled when depth test is enabled and
alpha test is disabled and fragment shader does not write
depth.
The early-z is implemented by moving the depth test stage
just before the fragment shader stage and prepending it
with an earlyz stage, introduced with this commit.
The earlyz stage prepares the quad->outputs.depth for
the following depth test stage by interpolating Z position,
just as the fragment shader would do.
2007-11-18 18:20:20 +00:00
Ben Skeggs
c7c6253169
nouveau: m2mf fallback path for region copies.
2007-11-18 23:08:33 +11:00
Ben Skeggs
f940603037
nv40: fix thinko == fix 3d textures
2007-11-18 22:12:50 +11:00
Ben Skeggs
a1d622190f
nv40: support TXP again
2007-11-18 21:47:18 +11:00
Ben Skeggs
3ab26c864c
nv40: some very rough guesses for get_paramf()
2007-11-18 17:59:45 +11:00
Ben Skeggs
bc449c28c6
nouveau: oops, when'd that disappear..
2007-11-18 17:49:30 +11:00
Ben Skeggs
2f33b5b56e
nouveau: Very rough cut at gallium winsys + nv40 pipe driver.
2007-11-18 17:34:06 +11:00
José Fonseca
ca7f68a7cf
Fix typo
2007-11-17 15:39:36 +00:00
José Fonseca
dec60d33b2
Proper fence reference counting.
2007-11-17 15:39:36 +00:00
Eric Anholt
f00a64999c
[intel] Add 965 support to shared intel_blit.c
...
This requires that regions grow a marker of whether they are tiled or not,
because fence (surface) registers are ignored by the 965 2D engine.
2007-11-16 17:29:30 -08:00
Eric Anholt
9b461d4d02
[i915] Pass static region names in so debugging says more than "static region".
2007-11-16 16:18:30 -08:00
Brian
34a00276c7
more convenient debug code
2007-11-16 17:13:26 -07:00
Brian
aa880bdfa0
Reimplement glRasterPos using the private 'draw' module.
2007-11-16 17:13:01 -07:00
Brian
6a1154bab0
adjustments so st_feedback_draw_vbo() can be used for glRasterPos
2007-11-16 17:12:22 -07:00
Eric Anholt
5ef6803b7a
[intel] Move additional code to be shared from intel_context.h to intel/.
2007-11-16 16:05:11 -08:00
Eric Anholt
5cdf3972de
[intel] Move intel_tex.h into place, forgotten in the previous commit.
2007-11-16 15:51:34 -08:00
Eric Anholt
8775bf475b
[965] Add batchbuffer decode for several more packets.
2007-11-16 15:44:11 -08:00
Eric Anholt
a66413874d
[intel] Fix typos in intel_chipset.h macros.
2007-11-16 15:36:18 -08:00
Eric Anholt
3bd07ba0d4
[i915] Add INTEL_DEBUG=sync debug flag to wait for fences after making them.
2007-11-16 15:36:18 -08:00
Eric Anholt
f7e0513d70
[i915] Reenable batchbuffer debug under INTEL_DEBUG=bat.
2007-11-16 15:36:18 -08:00
Eric Anholt
152aa6350d
[intel] Add some doxygen notes on what the bufmgr_fake block members mean.
2007-11-16 15:36:18 -08:00
Eric Anholt
c29e9e534e
[intel] Add a simple relocation cache to the fake buffer manager.
...
This is required for 965 performance, as it avoids a lot of repeated data
uploads of the state caches due to surface offsets in them.
2007-11-16 15:36:18 -08:00
Eric Anholt
4bc625e378
[intel] Assert against 0-sized buffers in dri_bufmgr_fake.c.
...
They shouldn't be created, and this often helps catch stupid issues.
2007-11-16 15:36:18 -08:00
Eric Anholt
00eb5635c6
[intel] Add support for multiple levels of relocation in bufmgr_fake.
...
This is required for 965 support, which has relocations in other places than
just the batchbuffer.
2007-11-16 15:36:18 -08:00
Eric Anholt
df3c530bed
[i915] Push locking in intelClearWithTris down inside meta_draw_poly.
...
The lock coverage and checks for cliprects were unneeded since the batchbuffer
will have INTEL_BATCH_CLIPRECTS anyway. It appeared to be a leftover from
intelClearWithBlit.
This makes the locking requirements of i915 meta_draw_quad match i965
meta_draw_quad.
2007-11-16 15:36:18 -08:00
Brian
8211b20026
added z/s keys to reset/step rotation
2007-11-16 15:19:05 -07:00
