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nouveau: update to latest header

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This commit is contained in:
Ben Skeggs 2007-11-20 13:22:11 +11:00
parent c7c6253169
commit 060127af38
5 changed files with 5877 additions and 5335 deletions
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65
src/mesa/drivers/dri/nouveau_winsys/nv04_region.c
View file

@ -6,9 +6,9 @@ static INLINE int
nv04_surface_format(int cpp)
{
switch (cpp) {
case 1: return 0x1;
case 2: return 0x4;
case 4: return 0xb;
case 1: return NV04_CONTEXT_SURFACES_2D_FORMAT_Y8;
case 2: return NV04_CONTEXT_SURFACES_2D_FORMAT_R5G6B5;
case 4: return NV04_CONTEXT_SURFACES_2D_FORMAT_Y32;
default:
return -1;
}
@ -18,9 +18,9 @@ static INLINE int
nv04_rect_format(int cpp)
{
switch (cpp) {
case 1: return 0x3;
case 2: return 0x1;
case 4: return 0x3;
case 1: return NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A8R8G8B8;
case 2: return NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A16R5G6B5;
case 4: return NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A8R8G8B8;
default:
return -1;
}
@ -78,8 +78,6 @@ nv04_region_copy(struct nouveau_context *nv, struct pipe_region *dst,
if (src->cpp != dst->cpp)
return 1;
NOUVEAU_ERR("preg\n");
/* NV_CONTEXT_SURFACES_2D has buffer alignment restrictions, fallback
* to NV_MEMORY_TO_MEMORY_FORMAT in this case.
*/
@ -96,10 +94,10 @@ nv04_region_copy(struct nouveau_context *nv, struct pipe_region *dst,
return 1;
}
BEGIN_RING(NvCtxSurf2D, 0x0184, 2);
BEGIN_RING(NvCtxSurf2D, NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_SOURCE, 2);
OUT_RELOCo(src->buffer, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
OUT_RELOCo(dst->buffer, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
BEGIN_RING(NvCtxSurf2D, 0x0300, 4);
BEGIN_RING(NvCtxSurf2D, NV04_CONTEXT_SURFACES_2D_FORMAT, 4);
OUT_RING (format);
OUT_RING (((dst->pitch * dst->cpp) << 16) | (src->pitch * src->cpp));
OUT_RELOCl(src->buffer, src_offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
@ -131,20 +129,21 @@ nv04_region_fill(struct nouveau_context *nv,
return 1;
}
BEGIN_RING(NvCtxSurf2D, 0x0184, 2);
BEGIN_RING(NvCtxSurf2D, NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_SOURCE, 2);
OUT_RELOCo(dst->buffer, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
OUT_RELOCo(dst->buffer, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
BEGIN_RING(NvCtxSurf2D, 0x0300, 4);
BEGIN_RING(NvCtxSurf2D, NV04_CONTEXT_SURFACES_2D_FORMAT, 4);
OUT_RING (cs2d_format);
OUT_RING (((dst->pitch * dst->cpp) << 16) | (dst->pitch * dst->cpp));
OUT_RELOCl(dst->buffer, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
OUT_RELOCl(dst->buffer, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
BEGIN_RING(NvGdiRect, 0x0300, 1);
BEGIN_RING(NvGdiRect, NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT, 1);
OUT_RING (gdirect_format);
BEGIN_RING(NvGdiRect, 0x03fc, 1);
BEGIN_RING(NvGdiRect, NV04_GDI_RECTANGLE_TEXT_COLOR1_A, 1);
OUT_RING (value);
BEGIN_RING(NvGdiRect, 0x0400, 2);
BEGIN_RING(NvGdiRect,
NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT(0), 2);
OUT_RING ((dx << 16) | dy);
OUT_RING (( w << 16) | h);
@ -164,6 +163,7 @@ nv04_region_data(struct nouveau_context *nv, struct pipe_region *dst,
int
nouveau_region_init_nv04(struct nouveau_context *nv)
{
unsigned class;
int ret;
if ((ret = nouveau_grobj_alloc(nv->channel, nv->next_handle++, 0x39,
@ -171,43 +171,48 @@ nouveau_region_init_nv04(struct nouveau_context *nv)
NOUVEAU_ERR("Error creating m2mf object: %d\n", ret);
return 1;
}
BEGIN_RING(NvM2MF, 0x0180, 1);
BEGIN_RING(NvM2MF, NV_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY, 1);
OUT_RING (nv->sync_notifier->handle);
if ((ret = nouveau_grobj_alloc(nv->channel, nv->next_handle++, 0x62,
class = nv->chipset < 0x10 ? NV04_CONTEXT_SURFACES_2D :
NV10_CONTEXT_SURFACES_2D;
if ((ret = nouveau_grobj_alloc(nv->channel, nv->next_handle++, class,
&nv->NvCtxSurf2D))) {
NOUVEAU_ERR("Error creating 2D surface object: %d\n", ret);
return 1;
}
BEGIN_RING(NvCtxSurf2D, 0x0184, 2);
BEGIN_RING(NvCtxSurf2D, NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_SOURCE, 2);
OUT_RING (nv->channel->vram->handle);
OUT_RING (nv->channel->vram->handle);
if ((ret = nouveau_grobj_alloc(nv->channel, nv->next_handle++, 0x9f,
class = nv->chipset < 0x10 ? NV_IMAGE_BLIT :
NV12_IMAGE_BLIT;
if ((ret = nouveau_grobj_alloc(nv->channel, nv->next_handle++, class,
&nv->NvImageBlit))) {
NOUVEAU_ERR("Error creating blit object: %d\n", ret);
return 1;
}
BEGIN_RING(NvImageBlit, 0x0180, 1);
BEGIN_RING(NvImageBlit, NV_IMAGE_BLIT_DMA_NOTIFY, 1);
OUT_RING (nv->sync_notifier->handle);
BEGIN_RING(NvImageBlit, 0x019c, 1);
BEGIN_RING(NvImageBlit, NV_IMAGE_BLIT_SURFACE, 1);
OUT_RING (nv->NvCtxSurf2D->handle);
BEGIN_RING(NvImageBlit, 0x02fc, 1);
OUT_RING (3);
BEGIN_RING(NvImageBlit, NV_IMAGE_BLIT_OPERATION, 1);
OUT_RING (NV_IMAGE_BLIT_OPERATION_SRCCOPY);
if ((ret = nouveau_grobj_alloc(nv->channel, nv->next_handle++, 0x4a,
class = NV04_GDI_RECTANGLE_TEXT;
if ((ret = nouveau_grobj_alloc(nv->channel, nv->next_handle++, class,
&nv->NvGdiRect))) {
NOUVEAU_ERR("Error creating rect object: %d\n", ret);
return 1;
}
BEGIN_RING(NvGdiRect, 0x0180, 1);
BEGIN_RING(NvGdiRect, NV04_GDI_RECTANGLE_TEXT_DMA_NOTIFY, 1);
OUT_RING (nv->sync_notifier->handle);
BEGIN_RING(NvGdiRect, 0x0198, 1);
BEGIN_RING(NvGdiRect, NV04_GDI_RECTANGLE_TEXT_SURFACE, 1);
OUT_RING (nv->NvCtxSurf2D->handle);
BEGIN_RING(NvGdiRect, 0x02fc, 1);
OUT_RING (3);
BEGIN_RING(NvGdiRect, 0x0304, 1);
OUT_RING (2);
BEGIN_RING(NvGdiRect, NV04_GDI_RECTANGLE_TEXT_OPERATION, 1);
OUT_RING (NV04_GDI_RECTANGLE_TEXT_OPERATION_SRCCOPY);
BEGIN_RING(NvGdiRect, NV04_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT, 1);
OUT_RING (NV04_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT_LE);
nv->region_display = nv04_region_display;
nv->region_copy = nv04_region_copy;

10925
src/mesa/pipe/nouveau/nouveau_class.h
View file

File diff suppressed because it is too large Load diff

122
src/mesa/pipe/nv40/nv40_state.c
View file

@ -119,21 +119,101 @@ nv40_blend_state_delete(struct pipe_context *pipe, void *hwcso)
free(hwcso);
}
static INLINE unsigned
wrap_mode(unsigned wrap) {
unsigned ret;
switch (wrap) {
case PIPE_TEX_WRAP_REPEAT:
ret = NV40TCL_TEX_WRAP_S_REPEAT;
break;
case PIPE_TEX_WRAP_MIRROR_REPEAT:
ret = NV40TCL_TEX_WRAP_S_MIRRORED_REPEAT;
break;
case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
ret = NV40TCL_TEX_WRAP_S_CLAMP_TO_EDGE;
break;
case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
ret = NV40TCL_TEX_WRAP_S_CLAMP_TO_BORDER;
break;
case PIPE_TEX_WRAP_CLAMP:
ret = NV40TCL_TEX_WRAP_S_CLAMP;
break;
case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
ret = NV40TCL_TEX_WRAP_S_MIRROR_CLAMP_TO_EDGE;
break;
case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
ret = NV40TCL_TEX_WRAP_S_MIRROR_CLAMP_TO_BORDER;
break;
case PIPE_TEX_WRAP_MIRROR_CLAMP:
ret = NV40TCL_TEX_WRAP_S_MIRROR_CLAMP;
break;
default:
NOUVEAU_ERR("unknown wrap mode: %d\n", wrap);
ret = NV40TCL_TEX_WRAP_S_REPEAT;
break;
}
return ret >> NV40TCL_TEX_WRAP_S_SHIFT;
}
static void *
nv40_sampler_state_create(struct pipe_context *pipe,
const struct pipe_sampler_state *cso)
{
struct nv40_sampler_state *ps;
uint32_t filter = 0;
ps = malloc(sizeof(struct nv40_sampler_state));
ps->wrap = ((nv40_tex_wrap_mode(cso->wrap_r) << 16) |
(nv40_tex_wrap_mode(cso->wrap_t) << 8) |
(nv40_tex_wrap_mode(cso->wrap_s) << 0));
ps->filt = ((nv40_tex_filter(cso->min_img_filter,
cso->min_mip_filter) << 16) |
(nv40_tex_filter(cso->mag_img_filter,
PIPE_TEX_MIPFILTER_NONE) << 24));
switch (cso->mag_img_filter) {
case PIPE_TEX_FILTER_LINEAR:
filter |= NV40TCL_TEX_FILTER_MAG_LINEAR;
break;
case PIPE_TEX_FILTER_NEAREST:
default:
filter |= NV40TCL_TEX_FILTER_MAG_NEAREST;
break;
}
switch (cso->min_img_filter) {
case PIPE_TEX_FILTER_LINEAR:
switch (cso->min_mip_filter) {
case PIPE_TEX_MIPFILTER_NEAREST:
filter |= NV40TCL_TEX_FILTER_MIN_LINEAR_MIPMAP_NEAREST;
break;
case PIPE_TEX_MIPFILTER_LINEAR:
filter |= NV40TCL_TEX_FILTER_MIN_LINEAR_MIPMAP_LINEAR;
break;
case PIPE_TEX_MIPFILTER_NONE:
default:
filter |= NV40TCL_TEX_FILTER_MIN_LINEAR;
break;
}
break;
case PIPE_TEX_FILTER_NEAREST:
default:
switch (cso->min_mip_filter) {
case PIPE_TEX_MIPFILTER_NEAREST:
filter |= NV40TCL_TEX_FILTER_MIN_NEAREST_MIPMAP_NEAREST;
break;
case PIPE_TEX_MIPFILTER_LINEAR:
filter |= NV40TCL_TEX_FILTER_MIN_NEAREST_MIPMAP_LINEAR;
break;
case PIPE_TEX_MIPFILTER_NONE:
default:
filter |= NV40TCL_TEX_FILTER_MIN_NEAREST;
break;
}
break;
}
ps->wrap = ((wrap_mode(cso->wrap_r) << NV40TCL_TEX_WRAP_S_SHIFT) |
(wrap_mode(cso->wrap_t) << NV40TCL_TEX_WRAP_T_SHIFT) |
(wrap_mode(cso->wrap_s) << NV40TCL_TEX_WRAP_R_SHIFT));
ps->filt = filter;
ps->bcol = ((float_to_ubyte(cso->border_color[3]) << 24) |
(float_to_ubyte(cso->border_color[0]) << 16) |
(float_to_ubyte(cso->border_color[1]) << 8) |
@ -497,33 +577,23 @@ nv40_set_framebuffer_state(struct pipe_context *pipe,
OUT_RING (rt_enable);
if (0) {
#if 0
rt_format |= (log2width <<
NV40TCL_RT_FORMAT_LOG2_WIDTH_SHIFT);
rt_format |= (log2height <<
NV40TCL_RT_FORMAT_LOG2_HEIGHT_SHIFT);
#endif
rt_format |= (NV40TCL_RT_FORMAT_TYPE_SWIZZLED <<
NV40TCL_RT_FORMAT_TYPE_SHIFT);
rt_format |= (0 << NV40TCL_RT_FORMAT_LOG2_WIDTH_SHIFT);
rt_format |= (0 << NV40TCL_RT_FORMAT_LOG2_HEIGHT_SHIFT);
rt_format |= NV40TCL_RT_FORMAT_TYPE_SWIZZLED;
} else {
rt_format |= (NV40TCL_RT_FORMAT_TYPE_LINEAR <<
NV40TCL_RT_FORMAT_TYPE_SHIFT);
rt_format |= NV40TCL_RT_FORMAT_TYPE_LINEAR;
}
if (fb->cbufs[0]->format == PIPE_FORMAT_U_R5_G6_B5) {
rt_format |= (NV40TCL_RT_FORMAT_COLOR_R5G6B5 <<
NV40TCL_RT_FORMAT_COLOR_SHIFT);
rt_format |= NV40TCL_RT_FORMAT_COLOR_R5G6B5;
} else {
rt_format |= (NV40TCL_RT_FORMAT_COLOR_A8R8G8B8 <<
NV40TCL_RT_FORMAT_COLOR_SHIFT);
rt_format |= NV40TCL_RT_FORMAT_COLOR_A8R8G8B8;
}
if (fb->zbuf && fb->zbuf->format == PIPE_FORMAT_U_Z16) {
rt_format |= (NV40TCL_RT_FORMAT_DEPTH_Z16 <<
NV40TCL_RT_FORMAT_DEPTH_SHIFT);
rt_format |= NV40TCL_RT_FORMAT_ZETA_Z16;
} else {
rt_format |= (NV40TCL_RT_FORMAT_DEPTH_Z24S8 <<
NV40TCL_RT_FORMAT_DEPTH_SHIFT);
rt_format |= NV40TCL_RT_FORMAT_ZETA_Z24S8;
}
BEGIN_RING(curie, NV40TCL_RT_HORIZ, 3);

51
src/mesa/pipe/nv40/nv40_state.h
View file

@ -119,55 +119,4 @@ struct nv40_depth_stencil_state {
} stencil;
};
static INLINE unsigned
nv40_tex_wrap_mode(unsigned wrap) {
switch (wrap) {
case PIPE_TEX_WRAP_REPEAT:
return NV40TCL_TEX_WRAP_S_REPEAT;
case PIPE_TEX_WRAP_MIRROR_REPEAT:
return NV40TCL_TEX_WRAP_S_MIRRORED_REPEAT;
case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
return NV40TCL_TEX_WRAP_S_CLAMP_TO_EDGE;
case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
return NV40TCL_TEX_WRAP_S_CLAMP_TO_BORDER;
case PIPE_TEX_WRAP_CLAMP:
return NV40TCL_TEX_WRAP_S_CLAMP;
case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
return NV40TCL_TEX_WRAP_S_MIRROR_CLAMP_TO_EDGE;
case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
return NV40TCL_TEX_WRAP_S_MIRROR_CLAMP_TO_BORDER;
case PIPE_TEX_WRAP_MIRROR_CLAMP:
return NV40TCL_TEX_WRAP_S_MIRROR_CLAMP;
default:
return NV40TCL_TEX_WRAP_S_REPEAT;
}
}
static INLINE unsigned
nv40_tex_filter(unsigned f0, unsigned f1) {
switch (f0) {
case PIPE_TEX_FILTER_NEAREST:
switch (f1) {
case PIPE_TEX_MIPFILTER_NEAREST:
return NV40TCL_TEX_FILTER_MIN_NEAREST_MIPMAP_NEAREST;
case PIPE_TEX_MIPFILTER_LINEAR:
return NV40TCL_TEX_FILTER_MIN_NEAREST_MIPMAP_LINEAR;
case PIPE_TEX_MIPFILTER_NONE:
default:
return NV40TCL_TEX_FILTER_MIN_NEAREST;
}
case PIPE_TEX_FILTER_LINEAR:
default:
switch (f1) {
case PIPE_TEX_MIPFILTER_NEAREST:
return NV40TCL_TEX_FILTER_MIN_LINEAR_MIPMAP_NEAREST;
case PIPE_TEX_MIPFILTER_LINEAR:
return NV40TCL_TEX_FILTER_MIN_LINEAR_MIPMAP_LINEAR;
case PIPE_TEX_MIPFILTER_NONE:
default:
return NV40TCL_TEX_FILTER_MIN_LINEAR;
}
}
}
#endif

49
src/mesa/pipe/nv40/nv40_state_tex.c
View file

@ -6,14 +6,10 @@
TRUE, \
PIPE_FORMAT_##m, \
NV40TCL_TEX_FORMAT_FORMAT_##tf, \
(NV40TCL_TEX_SWIZZLE_S0_X_##ts0x << NV40TCL_TEX_SWIZZLE_S0_X_SHIFT) | \
(NV40TCL_TEX_SWIZZLE_S0_X_##ts0y << NV40TCL_TEX_SWIZZLE_S0_Y_SHIFT) | \
(NV40TCL_TEX_SWIZZLE_S0_X_##ts0z << NV40TCL_TEX_SWIZZLE_S0_Z_SHIFT) | \
(NV40TCL_TEX_SWIZZLE_S0_X_##ts0w << NV40TCL_TEX_SWIZZLE_S0_W_SHIFT) | \
(NV40TCL_TEX_SWIZZLE_S1_X_##ts1x << NV40TCL_TEX_SWIZZLE_S1_X_SHIFT) | \
(NV40TCL_TEX_SWIZZLE_S1_X_##ts1y << NV40TCL_TEX_SWIZZLE_S1_Y_SHIFT) | \
(NV40TCL_TEX_SWIZZLE_S1_X_##ts1z << NV40TCL_TEX_SWIZZLE_S1_Z_SHIFT) | \
(NV40TCL_TEX_SWIZZLE_S1_X_##ts1w << NV40TCL_TEX_SWIZZLE_S1_W_SHIFT), \
(NV40TCL_TEX_SWIZZLE_S0_X_##ts0x | NV40TCL_TEX_SWIZZLE_S0_Y_##ts0y | \
NV40TCL_TEX_SWIZZLE_S0_Z_##ts0z | NV40TCL_TEX_SWIZZLE_S0_W_##ts0w | \
NV40TCL_TEX_SWIZZLE_S1_X_##ts1x | NV40TCL_TEX_SWIZZLE_S1_Y_##ts1y | \
NV40TCL_TEX_SWIZZLE_S1_Z_##ts1z | NV40TCL_TEX_SWIZZLE_S1_W_##ts1w), \
}
struct nv40_texture_format {
@ -53,20 +49,6 @@ nv40_tex_format(uint pipe_format)
return NULL;
}
static INLINE int
nv40_tex_dims(uint pipe_target)
{
switch (pipe_target) {
case PIPE_TEXTURE_1D: return 1;
case PIPE_TEXTURE_2D: return 2;
case PIPE_TEXTURE_3D: return 3;
case PIPE_TEXTURE_CUBE: return 2;
default:
NOUVEAU_ERR("AII unknown pipe target: %d\n", pipe_target);
return 2;
}
}
static void
nv40_tex_unit_enable(struct nv40_context *nv40, int unit)
{
@ -78,20 +60,33 @@ nv40_tex_unit_enable(struct nv40_context *nv40, int unit)
int swizzled = 0; /*XXX: implement in region code? */
tf = nv40_tex_format(mt->format);
if (!tf->defined) {
if (!tf || !tf->defined) {
NOUVEAU_ERR("Unsupported texture format: 0x%x\n", mt->format);
return;
}
txf = (tf->format | 0x80) << NV40TCL_TEX_FORMAT_FORMAT_SHIFT;
txf = tf->format | 0x8000;
txf |= ((mt->last_level - mt->first_level + 1) <<
NV40TCL_TEX_FORMAT_MIPMAP_COUNT_SHIFT);
if (1) /* XXX */
txf |= NV40TCL_TEX_FORMAT_NO_BORDER;
txf |= (nv40_tex_dims(mt->target) << NV40TCL_TEX_FORMAT_DIMS_SHIFT);
if (0) /*XXX*/
txf |= NV40TCL_TEX_FORMAT_RECT;
switch (mt->target) {
case PIPE_TEXTURE_2D:
case PIPE_TEXTURE_CUBE:
txf |= NV40TCL_TEX_FORMAT_DIMS_2D;
break;
case PIPE_TEXTURE_3D:
txf |= NV40TCL_TEX_FORMAT_DIMS_3D;
break;
case PIPE_TEXTURE_1D:
txf |= NV40TCL_TEX_FORMAT_DIMS_1D;
break;
default:
NOUVEAU_ERR("Unknown target %d\n", mt->target);
return;
}
if (swizzled) {
txp = 0;