We only want the atomic bit to be conditional to non sparse.
Also take the opportunity to fix buffer features and report the same
supported atomic formats as images.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: ed77f67e44 ("anv: add emulated 64bit integer storage support")
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35358>
(cherry picked from commit befc2a2f62)
The max dimensions are in units of pixels, not bytes. But the x
coordinate shift is based on aligning the address/offset to 64.
Rework the buffer clear loop to iterate in terms of pixels, but
with the x dimension shift based on converting aligned offset
to pixels.
Fixes OpenCL-CTS test_buffers.
Fixes: dafc4476f7 ("freedreno: Implement fast clear_buffer for Adreno 6xx and 7xx")
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35557>
(cherry picked from commit 8d13fc447e)
There were two issues with the current implementation:
- We didn't set the offset for sampler and image views
- Image::fill didn't take the parents offset into account
Cc: mesa-stable
Reported-by: Rob Clark <rob.clark@oss.qualcomm.com>
Tested-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35537>
(cherry picked from commit 7e9ee2000a)
Only GFX10+ can support 1x user sample locations, but MSAA_ENABLE
needs to be enabled.
Fixes new VKCTS coverage dEQP-VK.pipeline.*samples_1*.
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35492>
(cherry picked from commit 061bc6151a)
DCC tilings info needs to be set for all surfaces, including
depth/stencil. But because this is a C union, settings those fields
for depth/stencil surfaces might accidentally overwrite HiZ info.
This fixes rendering issues with RADV_DEBUG=nohiz.
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35515>
(cherry picked from commit 251b23f6c2)
The frontend does not know that etnaviv may keep multiple shadows around
for a resource, so it will always pass in the base resource as blit source
and destination. For those blits to work as expected by the API we need to
work out which shadow is the most recent one and use those as blit source
and destination resources.
CC: mesa-stable
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35526>
(cherry picked from commit ede41372f4)
etna_copy_resource() and etna_copy_resource_box() are used to keep the
internal shadow copies of a resource up to date. They are supposed to
always use the RS or BLT engines to do the copy, never requiring any
fallbacks or fake format handling. They should also work regardless of
the current render condition state. So instead of going through the
pipe_context blit hook, directly call the RS or BLT blit hook on the
etna_context.
CC: mesa-stable
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35526>
(cherry picked from commit d4780f03fc)
It was based on reverse engineering and inaccurate.
This also get ride of fp64 usage and will allow us to use it in OpenCL C
shaders for indirect/indexed draw.
On the full 32-bit range, this fixes ~10 millions inaccurate results.
Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Fixes: 467ae0d39d ("panfrost: Factor out panfrost_compute_magic_divisor")
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Olivia Lee <olivia.lee@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35490>
(cherry picked from commit b53d98eb41)
These return floating point types for floating point ops.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Backport-to: 25.1
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35489>
(cherry picked from commit 2ff53fd97c)
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: b49eab68a8 ("ac/nir: use s_sendmsg(HS_TESSFACTOR) to optimize writing tess factors for gfx11")
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35489>
(cherry picked from commit ac2e36b377)
This reverts commit 57ea689273.
This optimization is only sound when the operands of iadd are unsigned.
It turns out this is not always the case.
While the particular failure I was seeing was fixed by changing the
unsigned shifts to signed ones, I don't believe this is sound either. So
it's better to disable it for now until we find a better solution.
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Fixes: 57ea689273 ("ir3: optimize SSBO offset shifts for nir_opt_offsets")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34324>
(cherry picked from commit 29eb9ec7b7)
This prevents a regression from the next commit which would write
garbage for combined image+sampler descriptors and that might break
capture&replay.
It seems also more robust to write zeroes than garbage overall.
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35455>
(cherry picked from commit 22e06d65d7)
Do not perform a queue family ownership transfer during memory barriers
if srcQueueFamilyIndex equals dstQueueFamilyIndex, as the Vulkan spec
mandates that this should only happen if the two values are unequal.
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Fixes: 715d6e740a ("panvk: improve VK_QUEUE_FAMILY_EXTERNAL support")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35458>
(cherry picked from commit 5d0465a253)
The referenced commit was a step in the right direction, but not
complete.
ac_build_image_opcode returns a vec<4> or a struct<vec<4>, int>
so we can simplify visit_tex. We just need to map these 4/5 values
to the expected layout from NIR.
eg: depth + TFE would produces "<d, x, x, x>, t" so it has to be
transformed into <d, t>.
nir_texop_fragment_mask_fetch_amd + sparse doesn't exist, so it's
another opportunity for simplification.
This is required to get KHR-GL46.sparse_texture2_tests.SparseTexture2Lookup_texture_2d_depth_component16
working properly.
The same test fails with ACO so it probably needs a change in the
same area.
Fixes: c0ef2aa7f8 ("DEPENDENCY: ac/llvm: fix sparse code handling")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35206>
(cherry picked from commit 4a84ebfcb1)
If the clone_append was to a chunk of the same u_trace that gets
process_chunk()ed after where we're cloning from, then the payloads would
have been unreffed in the previous chunk's cleanup_chunk().
Fixes use-after-frees with turnip gmem rendering that resulted in
corrupted payloads.
Fixes: 14e45cb21e ("util/u_trace: refcount payloads")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35379>
(cherry picked from commit 6e97df1d76)
The previous fix 0cae8d372e is the right way to proceed, but it
should also apply when index_size is non-zero.
This change was tested on palm and cayman. Here is the test fixed:
spec/arb_multi_draw_indirect/arb_draw_elements_base_vertex-multidrawelements -indirect: fail pass
Fixes: 0cae8d372e ("r600: don't set an index_bias for indirect draw calls")
Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34726>
(cherry picked from commit a640b7233c)
The ISA docs don't mention this, but instead of always truncating
like other integer conversions, this opcode actually uses the single
precision rounding mode.
We could continue to use the opcode and set the rounding mode to rtz
in lower_to_hw_instrs, but I think I should just concede that f2u8
isn't worth the effort.
Fixes: 9bb10b58 ("aco: use v_cvt_pk_u8_f32 for f2u8")
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35391>
(cherry picked from commit d95e90ab5f)
We were allocating these, but never freeing the actual CSOs here.
Let's wire things up so we delete the data when we destroy the
hash-table. Because we don't have access to the context in that
callback, we can't call the pipe-level function to delete a CSO,
but luckily we don't actually need the context for the
driver-logic. So let's add an internal helper for that.
Fixes: ae3fb3089f ("panfrost: Add infrastructure for internal AFBC compute shaders")
Fixes: f39194cdd3 ("panfrost: support MTK 16L32S detiling")
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35336>
(cherry picked from commit fb0a422be2)
We were inserting twice here, once without holding the lock before
compiling the shaders, and once after while holding it. Let's remove
the insert without the lock.
Fixes: ae3fb3089f ("panfrost: Add infrastructure for internal AFBC compute shaders")
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35336>
(cherry picked from commit cc66651fc1)
This code sets PANFROST_JD_REQ_CYCLE_COUNT when using LD_GCLK to enable
shader_clock
Fixes: c1ce2dcc ("pan/bi: Enable ARB_shader_clock extension support")
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Signed-off-by: Ashley Smith <ashley.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35363>
(cherry picked from commit 95c508d950)
This is not a valid combination.
Fixes: 2dae926850 ("panfrost: add utils for AFRC fixed-rate support")
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Tested-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35015>
(cherry picked from commit b65b621062)
Not only the is_yuv() check in pan_afrc_get_format_info() didn't work,
because we use the multiplanar-RGB variants in panfrost, but we also
need the plane index to pick the right format.
Let's just assume AFRC(YUV) is not supported until someone decides to
add the necessary bits.
Fixes: 2dae926850 ("panfrost: add utils for AFRC fixed-rate support")
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Tested-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35015>
(cherry picked from commit bba62e047e)
