Rebuilding all the test containers for a change that only affects the
build containers is costly and unnecessary. Split the `DEBIAN_BASE_TAG`
into `DEBIAN_BUILD_BASE_TAG` and `DEBIAN_TEST_BASE_TAG` to make it
possible to rebuild only the relevant half of the containers.
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36736>
commandPools/cmdBuffers are only required for swapchain configurations
that use a blit-queue. They do not need to be allocated at all in the
"no blit" configuration.
There are some validUsage issues with the commandPool allocation, namely
that the WSI impl assumes that the logical device was created with all
queueFamilies made available to it. This is an invalid assumption that
can result in: VUID-vkCreateCommandPool-queueFamilyIndex-01937 invalid
usage on the eventual call to the driver. Note: invalid usage by WSI
wouldn't normally be detectable without virtualization.
This change reduces the scope of that invalid usage.
Reviewed-by: Gurchetan Singh <gurchetansingh@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36361>
Now that we lower all load_per_vertex_input to
r600_load_per_vertex_input we can remove some dead code
and also change the intrinsic to use only one source value.
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36488>
Extend the lowering of indirect GS array inputs to include
all indirect access. This replaces
r600_gs_load_deref_io_to_indirect_per_vertex_input
which was restricted to vec4 POS inputs. The
new lowering pass works in all vayings and all types, so we
can also drop the call to nir_lower_indirect_derefs.
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36488>
When the code is first generated constants are loaded to registers, so to
avoid indirect array register access that can be resolved as a direct direct
access we have to check whether the address register is loaded
with a constant value.
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36488>
nir_intrinsic_load_per_vertex_input has two source values, indirect access
by using the first value is already handled, but accessing arrays with
the second index was missing but became relevant with handling most IO
optimizations with nir_opt_varyings.
Fixes: 37ae4df3e4 ("glsl: remove most IO optimizations that are replaced by nir_opt_varyings")
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36488>
This is a preparation for the next patch that will fix
indirect access using the second index of load_per_vertex_input
Fixes: 37ae4df3e4 ("glsl: remove most IO optimizations that are replaced by nir_opt_varyings")
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36488>
In the case where gbm fails to init, we use our entire format list. That
became a problem in commit 642c4cf2b2 when some formats were added to the
list that X can't handle. This leads to X crashing when using glx and
trying to use certain visuals.
An easily testable manifestation of this crash is to run piglit's
glx-create-context-ext-no-config-context under Xwayland in a virtual
machine that has no gpu, whilst using zink. Much like our CI does for some
jobs.
Fixes: 642c4cf2b2 ("dril: add BGR{X,A}8888 and RGB{X,A}8888")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36575>
This disables HiZ on-demand when both depth/stencil are enabled and
depth writes are enabled to prevent potential issues.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36739>
HiZ is a separate image using standard image layout and tiling.
No need to support HiS which isn't available in any production chips.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36739>
util_perfetto_init() was called in some places, util_cpu_trace_init()
was called in other places, and some places used tracing without ever
calling either of them
util_cpu_trace_init() is now guaranteed to be called:
* on gallium screen create
* on VK instance create
thus no driver/frontend/etc should ever need to call this manually
cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36628>
Stage and access masks often go together. Representing the two
with a single value lets us have neater code.
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36176>
Currently the only thing this function ever does is clear AFBC
metadata when transitioning away from UNDEFINED.
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36176>
Make get_cs_deps accumulate the dependencies. This is useful when
implementing layout transitions. Layout transitions away from
UNDEFINED are implemented with a compute dispatch sandwiched
in-between src and dst, specified in the image barrier. When
implementing device event wait and the event dependency needs a
layout transition, we can defer emitting the barrier that syncs
layout transition dispatches with dst until after we have emitted
all dispatches, avoiding sync between the said transition
dispatches.
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36176>
vk_image_subresource_slice_count is useful when implementing image
barriers. When maintenance9 is enabled,
VkImageSubresourceRange::{baseArrayLayer,layerCount} specify the
slices, rather than layers, to transition. This helper returns
the number of slices specified in the subresource range, accounting
for the VK_REMAINING_ARRAY_LAYERS sentinel.
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36176>
This fixes an issue with Hellblade Senua's Sacrifice because
RADV_PERFTEST_RT_WAVE_64 is set using drirc, but if two devices are
created RADV_PERFTEST flags might differ.
The proposed solution is to filter out unused RADV_PERFTEST flags for
the winsys.
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36727>
GFX12 seems to behave slightly differently. Setting these bits to TRUE
causes zero-area triangles to not pass the primitive clipping stage.
So, the actual number of primitives output by the primitive clipping
stage was wrong.
After digging a lot, it seems PAL doesn't set these bits either on
GFX12.
CC: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36670>
We only do minimal checks to ensure that copy propagation doesn't break
the readport setup, but we don't update the groups readport setup. So
before scheduling the group do this update. Also check the readport
constellation when scheduling a group is finished.
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36572>
- If a readport reservation is not successful then we have to reset the
readport reservation.
- Since the scheduler can add instructions in any order, we have to
update the readports in the same order the slots were filled when
re-evaluating.
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36572>
Now that we track the free slots right away, we can make use of this
information when testing whether a vec instruction can be scheduled into
a trans slot.
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36584>
Lowering u2f64 and i2f64 will create such instructions and with that
the ALU groups are filled without the need to do scheduler trickery with
two-slot ops that have also two dest registers.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36587>
