r600/sfn: Simplify test code when scheduling a vec instr into trans
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Now that we track the free slots right away, we can make use of this
information when testing whether a vec instruction can be scheduled into
a trans slot.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36584>
This commit is contained in:
Gert Wollny 2025-06-19 23:08:45 +02:00 committed by Marge Bot
parent a6d97070a7
commit 9ce6d9ff1f

View file

@ -82,22 +82,21 @@ AluGroup::add_trans_instructions(AluInstr *instr)
if (instr->dest() && instr->dest()->pin() == pin_free) {
int used_slot = 3;
auto dest = instr->dest();
int free_mask = 0xf;
int possible_dest_channel_mask = m_free_slots ^ 0xf;
for (auto p : dest->parents()) {
auto alu = p->as_alu();
if (alu)
free_mask &= alu->allowed_dest_chan_mask();
possible_dest_channel_mask &= alu->allowed_dest_chan_mask();
}
for (auto u : dest->uses()) {
free_mask &= u->allowed_src_chan_mask();
if (!free_mask)
possible_dest_channel_mask &= u->allowed_src_chan_mask();
if (!possible_dest_channel_mask)
return false;
}
while (used_slot >= 0 &&
(!m_slots[used_slot] || !(free_mask & (1 << used_slot))))
while (used_slot >= 0 && (!(possible_dest_channel_mask & (1 << used_slot))))
--used_slot;
// if we schedule a non-trans instr into the trans slot,