fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-05 05:18:08 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 2

r600/sfn: Allow f2f64 to use vec2

Browse source 
Lowering u2f64 and i2f64 will create such instructions and with that
the ALU groups are filled without the need to do scheduler trickery with
two-slot ops that have also two dest registers.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36587>
This commit is contained in:
Gert Wollny 2025-08-07 22:55:11 +02:00 • committed by Marge Bot
parent fdaf105178
commit 6fea840c2c
1 changed files with 14 additions and 11 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

25
src/gallium/drivers/r600/sfn/sfn_instr_alu.cpp
View file

@ -2215,18 +2215,21 @@ emit_alu_f2f64(const nir_alu_instr& alu, Shader& shader)
auto group = new AluGroup();
AluInstr *ir = nullptr;
assert(alu.def.num_components == 1);
assert(alu.def.num_components < 3);
ir = new AluInstr(op1_flt32_to_flt64,
value_factory.dest(alu.def, 0, pin_chan),
value_factory.src(alu.src[0], 0),
AluInstr::write);
group->add_instruction(ir);
ir = new AluInstr(op1_flt32_to_flt64,
value_factory.dest(alu.def, 1, pin_chan),
value_factory.zero(),
AluInstr::last_write);
group->add_instruction(ir);
for (int i = 0; i < alu.def.num_components; ++i) {
ir = new AluInstr(op1_flt32_to_flt64,
value_factory.dest(alu.def, 2 * i, pin_chan),
value_factory.src(alu.src[0], 2 * i),
AluInstr::write);
group->add_instruction(ir);
ir = new AluInstr(op1_flt32_to_flt64,
value_factory.dest(alu.def, 2 * i + 1, pin_chan),
value_factory.zero(),
AluInstr::write);
group->add_instruction(ir);
}
ir->set_alu_flag(alu_last_instr);
shader.emit_instruction(group);
return true;
}