Commit graph

182751 commits

Author SHA1 Message Date
Pavel Ondračka
6167f6e096 r300: lower flrp in NIR
Shader-db RV370:
total instructions in shared programs: 82071 -> 82155 (0.10%)
instructions in affected programs: 792 -> 876 (10.61%)
helped: 0
HURT: 12
total temps in shared programs: 12775 -> 12778 (0.02%)
temps in affected programs: 27 -> 30 (11.11%)
helped: 0
HURT: 3
total cycles in shared programs: 128403 -> 128499 (0.07%)
cycles in affected programs: 864 -> 960 (11.11%)
helped: 0
HURT: 12

The same regression for the few GTK shaders that happens with the R500
nir fcsel lowering also happens here due to the
nir_move_vec_src_uses_to_dest.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6126
Reviewed-by: Filip Gawin <filip.gawin@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26816>
2024-01-04 08:02:00 +01:00
Pavel Ondračka
ddcf29202d r300: add some more early bool lowering
We can't call nir_lower_bool_to_float too early, because some other
passes like nir_opt_peephole_select will blow up, but we can still do
some selected parts to enable some optimiazions at a later point
(like fcsel(a,b,0) into fmul), etc.

No change in shader-db with RV370 or RV530 at this point.

Reviewed-by: Filip Gawin <filip.gawin@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26816>
2024-01-04 08:02:00 +01:00
Pavel Ondračka
024491f60f r300: nir fcsel/CMP lowering pass for R500
Right now this is done in the backend so move it up to NIR. Doing this
in the backend is easier, as at that time we can have a better idea
about when we hit the hardware limits of three different TMP sources,
however moving this to NIR allows for some optimizations. Specifically,
at this time if we decide we actually have to lower we still have the
info if we have plain fcsel for which we can save the comparison and
emit flrp only. During translation to TGSI all of fcsel, fcsel_gt, and
fcsel_ge translate to CMP so at that point the comparison is always needed.

Shader-db RV530:
total instructions in shared programs: 126057 -> 125823 (-0.19%)
instructions in affected programs: 11359 -> 11125 (-2.06%)
helped: 68
HURT: 12
total temps in shared programs: 17043 -> 17023 (-0.12%)
temps in affected programs: 459 -> 439 (-4.36%)
helped: 32
HURT: 12
total cycles in shared programs: 191604 -> 191294 (-0.16%)
cycles in affected programs: 11834 -> 11524 (-2.62%)
helped: 68
HURT: 12

The hurt shaders are some GTK shaders where there is some bad
interaction with nir_move_vec_src_uses_to_dest. This is known and might
be improved later by thweking the pass more.

Reviewed-by: Filip Gawin <filip.gawin@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26816>
2024-01-04 08:02:00 +01:00
Pavel Ondračka
75e7790ee5 r300: small adress register load optimization
We do ffloor by default for adress register load so no need to do it
explicitly. This needs to happen after int lowering, otherwise we get
ftrunc by default as a bonus. This is mostly for wined3d.

Shader-db RV370:
total instructions in shared programs: 82147 -> 82071 (-0.09%)
instructions in affected programs: 2772 -> 2696 (-2.74%)
helped: 32
HURT: 0
total cycles in shared programs: 128479 -> 128403 (-0.06%)
cycles in affected programs: 2813 -> 2737 (-2.70%)
helped: 32
HURT: 0

Shader-db RV530:
total instructions in shared programs: 126141 -> 126057 (-0.07%)
instructions in affected programs: 3170 -> 3086 (-2.65%)
helped: 36
HURT: 0
total cycles in shared programs: 191688 -> 191604 (-0.04%)
cycles in affected programs: 3222 -> 3138 (-2.61%)
helped: 36
HURT: 0

Reviewed-by: Filip Gawin <filip.gawin@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26816>
2024-01-04 08:02:00 +01:00
Dave Airlie
af3cca98a2 lavapipe: bump .maxResourceDescriptorBufferRange
Fail (maxResourceDescriptorBufferRange is less than (((1u << 20) - (1u << 15)) * maxResourceDescriptorSize) at vktBindingDescriptorBufferTests.cpp:5127)

bump this to pass the test now.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25398>
2024-01-04 03:58:23 +00:00
Dave Airlie
da53d0b6e5 gallivm/lp: move sampler index around to reduce struct
I'm not sure this is 100% correct, but it does reduce the
struct size to 256 which is conformant

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25398>
2024-01-04 03:58:23 +00:00
Dave Airlie
839045bcc8 gallivm/lp: merge sample info into normal info
multisample textures don't have mipmaps, so store sample_stride
into mipmap offset 15 and store num_samples into last_level

We can't use mipmap_offset0 as arrays might still store some values
into it.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25398>
2024-01-04 03:58:23 +00:00
Dave Airlie
344fa0895e gallivm/lp: reduce image descriptor size.
Reduce the image descriptor size alongside the texture one.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25398>
2024-01-04 03:58:23 +00:00
Dave Airlie
749a4fff86 gallivm/lp: reduce size of lp_jit_texture.
This is step one in a size reduction plan, this reduces lp_jit_texture
by making all the fields smaller in the struct and upsizing on the llvm
size. It goes from 280->264.

This isn't sufficient to get conformance, but it's a good step one.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25398>
2024-01-04 03:58:23 +00:00
Dave Airlie
1c68381ead gallivm/sample: make the load_mip helper useful outside this file.
Need this later for some size reduction patches.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25398>
2024-01-04 03:58:23 +00:00
Dave Airlie
bdde30c131 gallivm/sample: add some num_samples vs level zero only support
This just checks the level zero only is set for multisample stuff.

I tried using asserts, but there are paths due to precompilation
that won't get hit, but do get compiled.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25398>
2024-01-04 03:58:23 +00:00
Dave Airlie
7d4453b586 gallivm/sample: refactor first/last level handling and use level_zero_only.
This will help later esp for multisample textures which only ever have level 0

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25398>
2024-01-04 03:58:23 +00:00
Dmitry Baryshkov
c8c8c5a3cf freedreno/drm: don't crash in heap allocator when run under valgrind
If Mesa is executed under valgrind, fd_bo_init_common() calls
fd_bo_map() internally. For the heap (sub-block) allocator this causes a
segfault in fd_bo_map(), when this function tries to call the offset()
callback.

To prevent this from happening, preallocate fb->map before calling into
fd_bo_init_common(), stop calling VG_BO_ALLOC() if the memory map is
already initialised and disable the VG_BO_FREE call for the heap
allocator.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26277>
2024-01-04 03:17:46 +00:00
Dmitry Baryshkov
fd6b3bf267 freedreno/drm: notify valgrind about FD_BO_NOMAP maps
If the shader memory has been allocated with the FD_BO_NOMAP and got
later allocated a memory chunk during fd_bo_upload(), this can result in
the valgrind splat when it tries to release the free and/or cache the
BO. To fix this issue, notify valgrind about newly mmaped shader memory.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26277>
2024-01-04 03:17:46 +00:00
Dmitry Baryshkov
60686d4146 ir3/a6xx: fix ldg/stg of ulong2 and ulong4 data
Partially revert the commit f4c9e9329c ("ir3/a6xx: Fix immediate
offset stg/ldg path").

There is no need to multiply the immediate offsets by 4. Doing so
results in loading and/or storing the data at wrong locations.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26817>
2024-01-04 02:28:09 +00:00
Dmitry Baryshkov
3f25a73f17 ir3: fix shift amount for 8-bit shifts
Follow the 16-bit approach and convert shift amount to 8b for 8b shift
instructions.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26817>
2024-01-04 02:28:09 +00:00
Alyssa Rosenzweig
e7f3112eb9 asahi: Implement lod queries
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26861>
2024-01-04 01:51:07 +00:00
Alyssa Rosenzweig
d32daa3fb2 nir/validate: allow bias on nir_texop_lod
AGX seems to support it, and it's very convenient for implementing sampler LOD
bias together with a clamped LOD query.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26861>
2024-01-04 01:51:07 +00:00
VladimirTechMan
407fd1e1d7 venus/android: Switch to using u_gralloc
That enables testing and development of the Venus-based Vulkan HAL
on a wider range of Android systems - flavors of "Cuttlefish" are
of particular practical interest. At this point, only two gralloc
variants are supported: CrOS and IMapper v4. The fallback gralloc
and any gralloc adapter modules relying on it (GBM, QCOM) are out
of scope for Android Vulkan HAL now.

Signed-off-by: VladimirTechMan <VladimirTechMan@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26858>
2024-01-04 01:35:13 +00:00
Dave Airlie
c2f79d7fb1 llvmpipe: fix caching for texture shaders.
caching only works if you check the size and store the result,
later the size is always set.

Fixes: f675e4ee82 ("llvmpipe: Pre compile sample functions")
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25648>
2024-01-04 01:13:48 +00:00
Dave Airlie
8f73cc802c intel/compiler: revert part of "Move earlier scheduler code that is not mode-specific"
This removed a bunch of calls from the vec4 code that aren't called anywhere else.

Bring back the bits that were removed.

Fixes glxgears on gen5

Fixes: 81594d0db1 ("intel/compiler: Move earlier scheduler code that is not mode-specific")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26862>
2024-01-04 00:38:38 +00:00
Dave Airlie
37366fef68 intel/compiler: fix release build unused variable.
This is only used in an assert.

Fixes: 158ac265df ("intel/fs: Make helpers for saving/restoring instruction order")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26863>
2024-01-03 23:52:11 +00:00
Dave Airlie
b3cfec2fd8 gallivm: handle llvm 16 atexit ordering problems.
This is ported from amd ac_llvm_helper.cpp, thanks to Marek for the pointer.

This is needed to avoid crashes due to atexit ordering between some piglit
tests and mesa internals.

Cc: mesa-stable
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26883>
2024-01-03 22:57:17 +00:00
Rob Clark
2c078bfd18 freedreno/drm/virtio: Fix typo
Fixes: b90244776a ("virtio/drm: Split out common virtgpu drm structs")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26884>
2024-01-03 22:28:41 +00:00
Yonggang Luo
19fca131b1 amd: Use align64 instead of ALIGN for 64 bit value parameter
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26869>
2024-01-03 22:02:17 +00:00
Mike Blumenkrantz
49378bc3cd zink: enforce maxTexelBufferElements for texel buffer sizing
according to spec, creating larger texel buffers is legal for apps
but the resulting texel buffer must be clamped to device limits

fixes #10068

backport-to: 23.3

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26873>
2024-01-03 21:39:59 +00:00
Daniel Schürmann
bf43af984a nir/opt_loop_cf: generalize removal of "trivial" continues
So that is also handles break statements and works in
arbitrarily nested control flow.

Totals from 905 (1.18% of 76636) affected shaders: (RADV, GFX11)
Instrs: 605164 -> 605548 (+0.06%); split: -0.01%, +0.08%
CodeSize: 3162036 -> 3163472 (+0.05%); split: -0.01%, +0.06%
Latency: 2045559 -> 1387622 (-32.16%)
InvThroughput: 352344 -> 231676 (-34.25%)
SClause: 16092 -> 16088 (-0.02%); split: -0.04%, +0.02%
Copies: 41286 -> 41297 (+0.03%); split: -0.02%, +0.05%
Branches: 19949 -> 19929 (-0.10%)
PreSGPRs: 33413 -> 33385 (-0.08%)
PreVGPRs: 19177 -> 19135 (-0.22%)

Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24940>
2024-01-03 20:48:05 +00:00
Daniel Schürmann
bdbf873b0f nir: remove redundant passes from nir_opt_if()
These are now covered by nir_opt_loop():
- opt_if_loop_last_continue()
- opt_merge_breaks()
- opt_if_loop_terminator()

Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24940>
2024-01-03 20:48:05 +00:00
Daniel Schürmann
5b1b5cd794 nir: remove nir_opt_trivial_continues()
This pass is superseded by nir_opt_loop()

Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24940>
2024-01-03 20:48:04 +00:00
Daniel Schürmann
a3ed36da1a treewide: replace calls to nir_opt_trivial_continues() with nir_opt_loop()
Totals from 850 (1.11% of 76636) affected shaders: (RADV, GFX11)
MaxWaves: 18134 -> 18130 (-0.02%)
Instrs: 3011298 -> 3008585 (-0.09%); split: -0.17%, +0.08%
CodeSize: 15836804 -> 15841972 (+0.03%); split: -0.09%, +0.12%
VGPRs: 63580 -> 63604 (+0.04%)
SpillSGPRs: 966 -> 1148 (+18.84%); split: -0.83%, +19.67%
Latency: 36102291 -> 30186144 (-16.39%); split: -16.41%, +0.02%
InvThroughput: 9058100 -> 7011821 (-22.59%); split: -22.61%, +0.02%
VClause: 65369 -> 65364 (-0.01%); split: -0.03%, +0.02%
SClause: 100309 -> 100305 (-0.00%); split: -0.04%, +0.04%
Copies: 335658 -> 336472 (+0.24%); split: -0.70%, +0.94%
Branches: 110806 -> 108945 (-1.68%); split: -1.94%, +0.26%
PreSGPRs: 73476 -> 73934 (+0.62%); split: -0.25%, +0.87%
PreVGPRs: 58809 -> 58840 (+0.05%); split: -0.01%, +0.06%

Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24940>
2024-01-03 20:48:04 +00:00
Daniel Schürmann
9808ef0349 nir/opt_loop: move loop control-flow optimizations into separate pass
This new pass aims to simplify loop control-flow by reducing the number
of break and continue statements. It also supersedes nir_opt_trivial_continues().

For this purpose, it implements 3 optimizations:
- opt_loop_terminator(), as previously
- opt_loop_merge_break_continue(), similar to opt_merge_breaks() incl. continues
- opt_loop_last_block(), a generalization of opt_if_loop_last_continue()

Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24940>
2024-01-03 20:48:04 +00:00
Christian Gmeiner
0158075b22 nir/opt_peephole_select: handle speculative ubo loads
Some platforms may be able to speculate ubo loads safely.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8299>
2024-01-03 20:02:25 +00:00
Ruijing Dong
6c758000fb frontends/va: remove some TODOs in hevc encoding
Remove some TODOs in va hevc encoding sps parsing.

Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26770>
2024-01-03 19:23:08 +00:00
Karol Herbst
3ee6339206 clc: remove code supporting pre llvm-10
we require llvm-10+ already anyway, see meson.build:1726

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26871>
2024-01-03 18:30:32 +00:00
Danylo Piliaiev
99c69e624b freedreno: Disable UBWC for D/S images on A690
Mirrors workaround done for Turnip.

A690 seem to have broken UBWC for depth/stencil, it requires
depth flushing where we cannot realistically place it, like between
ordinary draw calls writing read/depth. WSL blob seem to use ubwc
sometimes for depth/stencil.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26226>
2024-01-03 17:35:07 +00:00
Danylo Piliaiev
fbfc1dc09d turnip: Disable UBWC for D/S images on A690
A690 seem to have broken UBWC for depth/stencil, it requires
depth flushing where we cannot realistically place it, like between
ordinary draw calls writing read/depth. WSL blob seem to use ubwc
sometimes for depth/stencil.

Some tests that this fixes:
 dEQP-VK.pipeline.monolithic.stencil.format.d24_unorm_s8_uint.states.fail_repl.pass_decw.dfail_inv.comp_never
 dEQP-VK.api.image_clearing.core.partial_clear_depth_stencil_attachment.single_layer.d32_sfloat_s8_uint_separate_layouts_depth_64x11
 dEQP-VK.api.image_clearing.dedicated_allocation.partial_clear_depth_stencil_attachment.single_layer.d16_unorm_33x128
 dEQP-VK.glsl.builtin_var.fragdepth.point_list_d32_sfloat_s8_uint_no_depth_clamp

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26226>
2024-01-03 17:35:07 +00:00
Danylo Piliaiev
9fcddb761b freedreno/devices: Update a690 magic regs from WSL blob
They don't seem to fix anything, but now that's values from driver
running on actual HW.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26226>
2024-01-03 17:35:07 +00:00
Sil Vilerino
e11605321a Revert "d3d12: Fix screen->winsys leak in d3d12_screen"
This reverts commit 81c8e89ff8.

Fixes: 81c8e89ff8 ("d3d12: Fix screen->winsys leak in d3d12_screen")
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26872>
2024-01-03 17:17:30 +00:00
Sil Vilerino
97cc7ea5a5 Revert "d3d12: Only destroy the winsys during screen destruction, not reset"
This reverts commit 325fb6e26b.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10371
Fixes: 325fb6e26b ("d3d12: Only destroy the winsys during screen destruction, not reset")
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26872>
2024-01-03 17:17:30 +00:00
daoxianggong
d6f0f46ae4 zink - Fix for blend color change without blend state change
Flag blend color change and make sure vkCmdSetBlendConstants is called.

Signed-off-by: daoxianggong <daoxiang.gong@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26799>
2024-01-03 16:35:51 +00:00
Gert Wollny
53efd35acc zink: Don't pass a blend state when we have full ds3 support
The blend state is considered to be dynamic when no
VkPipelineColorBlendStateCreateInfo  is passed in at pipeline creation.

Fixes:
 VUID-VkGraphicsPipelineCreateInfo-renderPass-06055 when running
  "Quern - Undying thoughts" when the GFX level enables blending.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26718>
2024-01-03 15:34:50 +00:00
Samuel Pitoiset
7ea48145a1 radv: stop clearing CMASK to 0xcc when FMASK is present on GFX9
This is incorrect because clearing CMASK to 0xCC should only happen
for fast clears with DCC and FMASK/CMASK.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26634>
2024-01-03 13:58:06 +00:00
Samuel Pitoiset
1714f7aff4 radv: disable FMASK for MSAA images with layers on GFX9
It seems that FMASK can be interleaved and RADV doesn't support this
properly, so let's disable it.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26634>
2024-01-03 13:58:06 +00:00
Rhys Perry
cad2c0915d aco/tests: use more raw strings
Python 3.12 started giving a SyntaxWarning for unrecognized escapes such
as "\w". This might become a SyntaxError in a future python version.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26850>
2024-01-03 13:33:52 +00:00
Yonggang Luo
472b6f5379 intel,crocus,iris: Use align64 instead of ALIGN for 64 bit value parameter
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26864>
2024-01-03 12:46:10 +00:00
Yonggang Luo
5a2aa3ff88 intel: Cleanup duplicate ALIGN macro defines
Use ALIGN function instead

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26864>
2024-01-03 12:46:10 +00:00
Yonggang Luo
8665ce27bc intel: Use ALIGN_POT instead of ALIGN inside macro define
These macro define is compute from literals, so use ALIGN_POT instead of ALIGN function
so that it's can be computed at compile time

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26864>
2024-01-03 12:46:10 +00:00
Yonggang Luo
3a9c569177 intel: Avoid use align as variable, replace it with other names
align is a function and when we want use it, the align variable will shadow it
So replace it with other names

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26864>
2024-01-03 12:46:10 +00:00
Samuel Pitoiset
10ce61e16c radv: advertise VK_KHR_maintenance6
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26757>
2024-01-03 11:24:27 +00:00
Samuel Pitoiset
db9816fd66 radv: add support for NULL index buffer
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26757>
2024-01-03 11:24:27 +00:00