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freedreno: Disable UBWC for D/S images on A690

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Mirrors workaround done for Turnip.

A690 seem to have broken UBWC for depth/stencil, it requires
depth flushing where we cannot realistically place it, like between
ordinary draw calls writing read/depth. WSL blob seem to use ubwc
sometimes for depth/stencil.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26226>
This commit is contained in:
Danylo Piliaiev 2023-11-16 15:55:42 +01:00 • committed by Marge Bot
parent fbfc1dc09d
commit 99c69e624b
1 changed files with 9 additions and 0 deletions
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9
src/gallium/drivers/freedreno/a6xx/fd6_resource.cc
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@ -68,6 +68,15 @@ ok_ubwc_format(struct pipe_screen *pscreen, enum pipe_format pfmt)
break;
}
/* A690 seem to have broken UBWC for depth/stencil, it requires
* depth flushing where we cannot realistically place it, like between
* ordinary draw calls writing read/depth. WSL blob seem to use ubwc
* sometimes for depth/stencil.
*/
if (info->a6xx.broken_ds_ubwc_quirk &&
util_format_is_depth_or_stencil(pfmt))
return false;
switch (fd6_color_format(pfmt, TILE6_LINEAR)) {
case FMT6_10_10_10_2_UINT:
case FMT6_10_10_10_2_UNORM_DEST: