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turnip: Disable UBWC for D/S images on A690

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A690 seem to have broken UBWC for depth/stencil, it requires
depth flushing where we cannot realistically place it, like between
ordinary draw calls writing read/depth. WSL blob seem to use ubwc
sometimes for depth/stencil.

Some tests that this fixes:
 dEQP-VK.pipeline.monolithic.stencil.format.d24_unorm_s8_uint.states.fail_repl.pass_decw.dfail_inv.comp_never
 dEQP-VK.api.image_clearing.core.partial_clear_depth_stencil_attachment.single_layer.d32_sfloat_s8_uint_separate_layouts_depth_64x11
 dEQP-VK.api.image_clearing.dedicated_allocation.partial_clear_depth_stencil_attachment.single_layer.d16_unorm_33x128
 dEQP-VK.glsl.builtin_var.fragdepth.point_list_d32_sfloat_s8_uint_no_depth_clamp

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26226>
This commit is contained in:
Danylo Piliaiev 2023-11-16 14:19:46 +01:00 • committed by Marge Bot
parent 9fcddb761b
commit fbfc1dc09d
3 changed files with 17 additions and 1 deletions
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3
src/freedreno/common/freedreno_dev_info.h
View file

@ -168,6 +168,9 @@ struct fd_dev_info {
bool supports_double_threadsize;
bool has_sampler_minmax;
bool broken_ds_ubwc_quirk;
struct {
uint32_t PC_POWER_CNTL;
uint32_t TPL1_DBG_ECO_CNTL;

6
src/freedreno/common/freedreno_devices.py
View file

@ -403,6 +403,10 @@ a6xx_gen4 = A6XXProps(
has_per_view_viewport = True,
)
a6xx_a690_quirk = A6XXProps(
broken_ds_ubwc_quirk = True,
)
add_gpus([
GPUId(605), # TODO: Test it, based only on libwrapfake dumps
GPUId(608), # TODO: Test it, based only on libwrapfake dumps
@ -710,7 +714,7 @@ add_gpus([
GPUId(chip_id=0xffff06090000, name="FD690"), # Default no-speedbin fallback
], A6xxGPUInfo(
CHIP.A6XX,
[a6xx_base, a6xx_gen4],
[a6xx_base, a6xx_gen4, a6xx_a690_quirk],
num_ccu = 8,
tile_align_w = 64,
tile_align_h = 32,

9
src/freedreno/vulkan/tu_image.cc
View file

@ -349,6 +349,15 @@ ubwc_possible(struct tu_device *device,
return false;
}
/* A690 seem to have broken UBWC for depth/stencil, it requires
* depth flushing where we cannot realistically place it, like between
* ordinary draw calls writing read/depth. WSL blob seem to use ubwc
* sometimes for depth/stencil.
*/
if (info->a6xx.broken_ds_ubwc_quirk &&
vk_format_is_depth_or_stencil(format))
return false;
/* Disable UBWC for D24S8 on A630 in some cases
*
* VK_IMAGE_ASPECT_STENCIL_BIT image view requires to be able to sample