The ambiguity of the Vulkan spec was clarified, and we don't need to
support sparse depth/stencil with exactly the same number of samples
as non-sparse.
If you want to pass CTS, you'll need VK-GL-CTS commit 03976477f521
("Don't require more than VK_SAMPLE_COUNT_1_BIT for non-color sparse
resident images").
This is essentially a revert of d5da6980d3 ("anv/sparse: don't
support depth/stencil with sparse") and 7b337e214d ("anv: remove
dead code").
Thanks to Iván Briano for working with Khronos to get clarification on
the spec and for implementing the VK-GL-CTS fix.
Reviewed-by: Iván Briano <ivan.briano@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37423>
While Jay overwrites sparse_tex->op with the newer opcodes that only
return red and the sparse stuff, BRW keeps using the original opcode
of the cloned instruction, so it can't change def->num_components.
This was not previously detectable since we did not have sparse
enabled for depth/stencil on Anv for a while. A patch to re-enable
that was proposed a while ago (MR !37423), never merged, but then a
recent attempt to try to merge it (by me) detected this regression.
Let's fix the regression first, then we can finally re-enable sparse
depth/stencil support in Anv, hopefully.
Fixes: 7468261d3d ("intel/nir: Make intel_nir_lower_sparse work for either brw or jay")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37423>
If we're a bit clever with the bits, we can make one fixup helper that
works for all rounding modes. See the giant comment for details.
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41295>
This makes the tests names a bit more consistent and takes advantage of
the namespacing that gtest already gives us. (There's no reason to put
the whole prefix in the test name again.)
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41295>
Smashing bits is super sketchy. However, all the bits do is force the
test down the _slow path so let's explicitly test that instead.
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41295>
This prints the swizzle pattern for all non-XOR tiling modes.
It can be used to determine which GPUs have the same tiling.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41405>
nir_opt_shrink_vectors narrows vector widths when only a subset of
components are consumed, which eliminates unnecessary cross-register
vec constructions. Follow with copy_prop + dce to clean up.
shader-db (I915_FS=nir): 272/403 compiled, 4388 alu
shader-db (I915_FS=both): nir won 272 (26 identical, 1 tied, 239 better, 6 only),
18 TGSI, 113 neither
Assisted-by: Claude
Some shaders produce better code when fully scalarized after
optimization: vec3(a, b, 1.0) feeding a dot product creates a
cross-register vec construction, but scalarizing the fmul exposes
1.0*1.0 to constant folding, eliminating the vec entirely.
Other shaders are worse fully scalar because corm's vec construction
handles same_reg vecs at zero cost. Add late_scalar as a variant
dimension so the multi-variant framework picks whichever is better
per shader.
shader-db (I915_FS=nir): 254/403 compiled, 4063 alu
shader-db (I915_FS=both): nir won 254 (26 identical, 1 tied, 221 better, 6 only),
36 TGSI, 113 neither
Assisted-by: Claude
Generalize the binary ALU consumer fusion to handle ffma (MAD) and
any number of inputs. When a vec's only consumer is an ALU op where
the vec occupies one source slot and all other sources are single
registers, emit the ALU op per register group with partial
writemasks.
shader-db (I915_FS=nir): 252/403 compiled, 3618 alu
shader-db (I915_FS=both): nir won 252 (26 identical, 1 tied, 219 better, 6 only),
38 TGSI, 113 neither
Assisted-by: Claude
When a vec construction feeds a single-use tex instruction, use a
utemp (unpreserved temp) instead of an R-file temp for the vec dest.
R-file temps written by ALU trigger tex indirect phase boundaries
when read by subsequent texld instructions; utemps do not.
Preserve the utemp allocation across i915_release_utemps so the
value survives until the texld consumer reads it.
shader-db (I915_FS=nir): 249/403 compiled, 3495 alu
shader-db (I915_FS=both): nir won 249 (26 identical, 1 tied, 217 better, 5 only),
40 TGSI, 114 neither
Assisted-by: Claude
When a vec's only consumer is a binary ALU op (MUL, ADD, MIN, MAX)
and the other source is a single register, emit the ALU op directly
per register group with partial writemasks instead of building the
vec with MOVs and then applying the ALU op.
For example, fmul(vec4(a.zw, b.xy), tex) becomes:
MUL oC.xy, a.zw, tex
MUL oC.zw, b.xy, tex
instead of:
MOV R.xy, a.zw
MOV R.zw, b.xy
MUL oC, R, tex
shader-db (I915_FS=nir): 248/403 compiled, 3544 alu
shader-db (I915_FS=both): nir won 248 (26 identical, 1 tied, 218 better, 3 only),
39 TGSI, 116 neither
Assisted-by: Claude
Generalize the scalar ALU dest fold to handle multi-component results.
When a vec source covers contiguous channels with identity swizzle and
all uses of the source come from this vec, patch the ALU instruction
to write directly into the vec's dest register with the appropriate
channel mask.
This eliminates redundant MOVs for patterns like
vec4(%result.x, %result.y, %result.z, %other)
where %result is a vec3 ALU output — the ALU instruction now writes
directly to the output register's .xyz channels.
shader-db (I915_FS=nir): 233/403 compiled, 3328 alu
shader-db (I915_FS=both): nir won 233 (26 identical, 1 tied, 203 better, 3 only),
54 TGSI, 116 neither
Assisted-by: Claude
When a vec2/3/4 construction has a single consumer that is a
store_output, emit the partial-writemask MOVs directly to the
output register (oC/oD) instead of building in a temp and copying.
Skip this for the same_reg case which already collapses to a
zero-instruction swizzle alias.
Also fix TGSI-win reporting: preserve loser stats before freeing
so corm_win_reason shows the actual delta instead of "only".
shader-db (I915_FS=nir): 214/403 compiled, 3231 alu
shader-db (I915_FS=both): nir won 214 (26 identical, 1 tied, 184 better, 3 only),
73 TGSI, 116 neither
Assisted-by: Claude
When a vec3 or vec4 load_const has all components from {0, 1, -1},
emit a swizzle+negate alias using the hardware ZERO/ONE source
constants instead of allocating a constant register via
i915_emit_const4fv. This matches what the TGSI path does through
its immediate recognition.
Saves a constant register slot per qualifying load_const and
converts 32 of 33 previous ties to identical output.
shader-db (I915_FS=nir): 212/403 compiled, 3227 alu
shader-db (I915_FS=both): nir won 212 (26 identical, 1 tied, 182 better, 3 only),
75 TGSI, 116 neither
Assisted-by: Claude
When opts.seq_sne_opt is set and one operand is zero, use the
abs+compare pattern: x == 0 becomes -abs(x) >= 0, and x != 0
becomes -abs(x) < 0. This reduces from 3 ALU instructions to 2.
This is a variant dimension because it can increase register
pressure in some shaders; the multi-variant framework picks the
winner per-shader.
shader-db (I915_FS=nir): 212/403 compiled, 3228 alu
shader-db (I915_FS=both): nir won 212 (26 identical, 16 tied, 167 better, 3 only),
75 TGSI, 116 neither
Assisted-by: Claude
When opts.deferred_const is set, defer scalar load_const allocation
until the consuming ALU instruction. coalesce_constants resolves
deferred constants with a preferred register hint so co-occurring
constants pack into the same CONST register, avoiding dual-constant
MOV penalties.
Also fix per-channel UBO constant flags: mark only the actually
loaded channels with I915_CONSTFLAG_USER_CH(comp+i) instead of
setting all user bits, leaving free channels for immediates.
shader-db (I915_FS=nir): 210/403 compiled, 3202 alu
shader-db (I915_FS=both): nir won 210 (26 identical, 16 tied, 165 better, 3 only),
77 TGSI, 116 neither
Assisted-by: Claude
Add the def_csr mechanism: track the instruction cursor position for
each single-instruction SSA def so we can retroactively patch it.
fsat folding: when a single-use SSA def feeds into fsat, fold
A0_DEST_SATURATE into the previous instruction instead of emitting
a separate MOV.
Output dest folding: when store_output consumes a single-use temp,
patch the previous instruction to write directly to the output
register (OC/OD). Includes vec look-through for the identity-swizzle
case where a vec was collapsed to a register alias.
Vec dest folding: single-use scalar ALU results feeding a vec
component get patched to write directly into the vec dest register.
shader-db (I915_FS=nir): 209/403 compiled, 3157 alu
shader-db (I915_FS=both): nir won 209 (26 identical, 16 tied, 164 better, 3 only),
78 TGSI, 116 neither
Assisted-by: Claude
Optimize vec2/3/4 construction with several strategies:
- same_reg: when all components come from the same register, collapse
to a single swizzle+negate alias (zero instructions)
- const-swizzle piggybacking: ZERO/ONE sources share a MOV with
real-register sources from the same register
- per-channel negate: preserve per-channel negate bits through the
swizzle path instead of emitting separate negation
shader-db (I915_FS=nir): 130/403 compiled, 1614 alu
shader-db (I915_FS=both): nir won 130 (26 identical, 16 tied, 86 better, 2 only),
156 TGSI, 117 neither
Assisted-by: Claude
Track the last use of each SSA def and release temporary registers
as soon as they're dead, allowing more aggressive temp reuse.
Includes the register aliasing fix for mov/fneg: these ops alias
the def to the source register, so the source's lifetime must be
extended to match the def's to prevent premature release.
shader-db (I915_FS=nir): 52/403 compiled, 231 alu
shader-db (I915_FS=both): nir won 52 (26 identical, 16 tied, 9 better, 1 only),
233 TGSI, 118 neither
Assisted-by: Claude
Bare-minimum NIR-to-i915 fragment shader compiler with multi-variant
framework, lexicographic cost metric (ALU > tex_indirect > temps > consts),
and winner-tagged stats output.
Stats are emitted once per shader with [NIR] or [TGSI] tag indicating
which backend won. The corm_compile_opts struct is available for
multi-variant compilation (currently empty).
Assisted-by: Claude
shader-db (I915_FS=nir): 48/403 compiled, 65 alu
shader-db (I915_FS=both): nir won 48 (26 identical, 16 tied, 6 better),
236 TGSI, 119 neither
Rework the constant register encoding to track per-channel ownership
(I915_CONSTFLAG_IMM / I915_CONSTFLAG_USER_CH) instead of whole-register
flags, allowing compiler immediates and user UBO values to share a
constant register on different channels. Update emit_constants() to
handle per-channel source selection at upload time.
Add i915_emit_const1f_prefer() for packing scalar constants into a
preferred register, reducing dual-constant conflicts.
Move i915_program_error(), i915_use_passthrough_shader(), and negate()
from i915_fpc_translate.c to shared locations (i915_fpc_emit.c /
i915_fpc.h) so the NIR backend can use them.
Fix i915_emit_texld() to use a utemp instead of a temp register for
texcoord swizzle copies, avoiding unnecessary tex indirect phase
boundaries. Add a fallback path that copies to a utemp when bumping
the phase count would exceed the hardware limit.
Add nr_alu_insn, nr_tex_insn, nr_tex_indirect, nr_temps, writes_z,
and input semantic tracking to i915_fragment_shader for use by the
NIR backend's multi-variant comparison framework.
Assisted-by: Claude
i915_fpc_optimize_mov_before_tex replaces a MOV+TEX pair with a
direct TEX from the input register when the MOV copies from the
input with identity swizzle. But it only checked the source swizzle,
not the MOV's writemask. When the MOV wrote a subset of the channels
the TEX reads (e.g., MOV TEMP.y, IN.y before a 2D TEX that reads
XY), the optimization replaced the TEX source with IN, losing the X
channel that was set by a different MOV.
This caused incorrect texture sampling coordinates in shaders with
multi-MOV texcoord construction (blur filters, shadow maps, etc.).
Fix: verify the MOV's dest writemask covers all channels the TEX
instruction reads before applying the optimization.
Assisted-by: Claude
The TGSI compiler rejected empty fragment shaders (num_instructions
== 1, just TGSI_END) as errors. Instead, emit a passthrough program.
Assisted-by: Claude
Report actual instruction counts (alu+tex) instead of program dwords/3,
add a separate "alu" field for the 64-instruction bottleneck metric, and
fix "temps" to use the actual temp register count instead of
util_last_bit (highest register number).
Before: "69 inst, 2 tex, 3 tex_indirect, 4 temps, 5 const"
After: "21 instructions, 19 alu, 2 tex, 2 tex_indirect, 16 temps, 3 const"
Assisted-by: Claude
draw_vs.c already handles the non-native-integer NIR→TGSI conversion
internally, so i915 doesn't need to do it. keep nir_lower_point_size
(i915-specific lowering) and pass the result to draw as NIR.
Assisted-by: Claude
Synchronize it with the values it actually accepts right now.
v2: Other values were added by other patches after I wrote this one.
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41277>
These options were replaced by ANV_DEBUG=no-sparse and
ANV_DEBUG=sparse-trtt in April of 2025, by 789f13359a ("anv:
consolidate environment variables"). The ANV_DEBUG versions are
already documented.
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41277>
This can only happen with RADV_DEBUG=fullsync which literally flushes
all caches, but INV_ICACHE is invalid with RELEASE_MEM apparently.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41396>
This removes 18042479026 as we don't utilize BRW_AOP_MOV in compiler
and adds missing xe2 entries for 14025112257.
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41281>
The common Mesa Vulkan WSI code checks some DRI options.
Add them to the option list of the PVR driver.
Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
Reviewed-by: Simon Perretta <simon.perretta@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41197>
The DRI options list is formatted specically and clang-format cannot
handle it properly.
Disable clang-format for this snippet.
Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
Reviewed-by: Simon Perretta <simon.perretta@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41197>
Bringing force_vk_vendor as the first option, force_vk_devicename
will be added later
Signed-off-by: hmtheboy154 <buingoc67@gmail.com>
Reviewed-by: Simon Perretta <simon.perretta@imgtec.com>
[Icenowy: rebased on top of main]
Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41197>
