mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
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amd: add a tool that prints tiling layouts for all shim devices
This prints the swizzle pattern for all non-XOR tiling modes. It can be used to determine which GPUs have the same tiling. Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41405>
This commit is contained in:
Marek Olšák
Marge Bot
parent
45706d39ea
commit
c6ddfe1a3b
2 changed files with 431 additions and 0 deletions
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@ -242,6 +242,17 @@ executable(
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build_by_default: with_tools.contains('amd')
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)
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executable(
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'ac_print_tiling_layouts',
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['tools/ac_print_tiling_layouts.c', 'amdgpu_devices.c'],
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link_with: [libamd_common],
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include_directories : [
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inc_amd, inc_include, inc_src,
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],
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dependencies : [idep_amd_generated_headers, idep_mesautil, idep_nir_headers],
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build_by_default: with_tools.contains('amd')
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)
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if with_tests and not with_platform_windows
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test(
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'ac_surface_modifier_test',
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420
src/amd/common/tools/ac_print_tiling_layouts.c
Normal file
420
src/amd/common/tools/ac_print_tiling_layouts.c
Normal file
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@ -0,0 +1,420 @@
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/* Copyright 2026 Valve Corporation
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* SPDX-License-Identifier: MIT
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*/
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#include <stdbool.h>
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#include <stdlib.h>
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#include "util/macros.h"
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#include "util/u_math.h"
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#include "amdgpu_devices.h"
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#include "amdgfxregs.h"
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#include "addrlib/inc/addrinterface.h"
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#define addr_check(call) do { \
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int r = call; \
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if (r) { \
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fprintf(stderr, "%s failed. (error = %u)\n", #call, r); \
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exit(1); \
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} \
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} while (0)
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static void *ADDR_API allocSysMem(const ADDR_ALLOCSYSMEM_INPUT *pInput)
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{
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return malloc(pInput->sizeInBytes);
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}
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static ADDR_E_RETURNCODE ADDR_API freeSysMem(const ADDR_FREESYSMEM_INPUT *pInput)
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{
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free(pInput->pVirtAddr);
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return ADDR_OK;
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}
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static uint32_t
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get_register_value(const struct amdgpu_device *dev, unsigned reg)
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{
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for (unsigned i = 0; i < dev->mmr_reg_count; i++) {
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if (dev->mmr_regs[i * 3] == reg / 4)
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return dev->mmr_regs[i * 3 + 2];
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}
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UNREACHABLE("invalid reg");
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}
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static ADDR_HANDLE
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addrlib_create(const struct amdgpu_device *dev)
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{
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unsigned gfx_version = dev->hw_ip_gfx.hw_ip_version_major;
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uint32_t mc_arb_ramcfg = 0;
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uint32_t gb_tile_mode[32] = {0};
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uint32_t gb_macrotile_mode[32] = {0};
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if (gfx_version < 9) {
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mc_arb_ramcfg = get_register_value(dev, 0x9D8 * 4);
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for (unsigned i = 0; i < 32; i++)
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gb_tile_mode[i] = get_register_value(dev, R_009910_GB_TILE_MODE0 + i * 4);
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if (gfx_version >= 7) {
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for (unsigned i = 0; i < 16; i++)
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gb_macrotile_mode[i] = get_register_value(dev, R_009990_GB_MACROTILE_MODE0 + i * 4);
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}
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}
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const unsigned CIASICIDGFXENGINE_SOUTHERNISLAND = 0xA;
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const unsigned CIASICIDGFXENGINE_ARCTICISLAND = 0xD;
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ADDR_CREATE_INPUT create_info = {
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.size = sizeof(create_info),
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.chipEngine = gfx_version < 9 ? CIASICIDGFXENGINE_SOUTHERNISLAND :
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CIASICIDGFXENGINE_ARCTICISLAND,
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.chipFamily = dev->dev.family,
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.chipRevision = dev->dev.external_rev,
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.callbacks = {
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.allocSysMem = allocSysMem,
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.freeSysMem = freeSysMem,
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},
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.createFlags = {
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.useTileIndex = gfx_version < 9,
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},
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.regValue = {
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.gbAddrConfig = get_register_value(dev, R_0098F8_GB_ADDR_CONFIG),
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.backendDisables = gfx_version < 9 ? dev->dev.enabled_rb_pipes_mask : 0,
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.noOfBanks = gfx_version < 9 ? mc_arb_ramcfg & 0x3 : 0,
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.noOfRanks = gfx_version < 9 ? (mc_arb_ramcfg & 0x4) >> 2 : 0,
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.pTileConfig = gfx_version < 9 ? gb_tile_mode : NULL,
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.noOfEntries = 32,
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.pMacroTileConfig = gfx_version >= 7 && gfx_version < 9 ? gb_macrotile_mode : NULL,
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.noOfMacroEntries = gfx_version >= 7 && gfx_version < 9 ? 16 : 0,
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},
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};
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ADDR_CREATE_OUTPUT lib = {
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.size = sizeof(lib),
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};
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addr_check(AddrCreate(&create_info, &lib));
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return lib.hLib;
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}
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#define DIPLAYABLE BITFIELD_BIT(5)
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typedef struct {
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unsigned tile_mode_index;
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} legacy_tile_info;
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static void
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get_tile_size(ADDR_HANDLE hlib, unsigned gfx_version, unsigned bpp, unsigned swizzle_mode,
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unsigned *tile_width, unsigned *tile_height, legacy_tile_info *legacy_info)
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{
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AddrFormat format;
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switch (bpp) {
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case 8:
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format = ADDR_FMT_8;
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break;
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case 16:
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format = ADDR_FMT_8_8;
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break;
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case 32:
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format = ADDR_FMT_8_8_8_8;
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break;
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case 64:
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format = ADDR_FMT_16_16_16_16;
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break;
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default:
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UNREACHABLE("invalid bpp");
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}
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/* We only need the tile size from this. */
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if (gfx_version >= 12) {
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ADDR3_COMPUTE_SURFACE_INFO_INPUT in = {
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.size = sizeof(in),
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.flags = {{0}},
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.swizzleMode = swizzle_mode,
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.resourceType = ADDR_RSRC_TEX_2D,
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.format = format,
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.bpp = bpp,
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.width = 4096,
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.height = 4096,
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.numSlices = 1,
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.numMipLevels = 1,
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.numSamples = 1,
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.pitchInElement = 4096,
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};
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ADDR3_COMPUTE_SURFACE_INFO_OUTPUT out = {
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.size = sizeof(out),
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};
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addr_check(Addr3ComputeSurfaceInfo(hlib, &in, &out));
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*tile_width = out.blockExtent.width;
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*tile_height = out.blockExtent.height;
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assert(out.blockExtent.depth == 1);
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} else if (gfx_version >= 9) {
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ADDR2_COMPUTE_SURFACE_INFO_INPUT in = {
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.size = sizeof(in),
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.flags = {
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.color = 1,
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},
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.swizzleMode = swizzle_mode,
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.resourceType = ADDR_RSRC_TEX_2D,
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.format = format,
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.bpp = bpp,
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.width = 4096,
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.height = 4096,
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.numSlices = 1,
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.numMipLevels = 1,
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.numSamples = 1,
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.numFrags = 1,
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.pitchInElement = 4096,
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};
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ADDR2_COMPUTE_SURFACE_INFO_OUTPUT out = {
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.size = sizeof(out),
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};
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addr_check(Addr2ComputeSurfaceInfo(hlib, &in, &out));
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*tile_width = out.blockWidth;
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*tile_height = out.blockHeight;
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assert(out.blockSlices == 1);
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} else {
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AddrTileMode mode = swizzle_mode & ~DIPLAYABLE;
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bool display = !!(swizzle_mode & DIPLAYABLE);
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ADDR_TILEINFO tile_info = {0};
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ADDR_COMPUTE_SURFACE_INFO_INPUT in = {
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.size = sizeof(in),
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.tileMode = mode,
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.format = format,
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.bpp = bpp,
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.numSamples = 1,
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.width = 4096,
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.height = 4096,
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.numSlices = 1,
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.numMipLevels = 1,
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.flags = {
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.color = 1,
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.display = display,
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.prt = mode == ADDR_TM_PRT_TILED_THIN1 ||
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mode == ADDR_TM_PRT_2D_TILED_THIN1,
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},
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.numFrags = 1,
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.tileType = display ? ADDR_DISPLAYABLE : ADDR_NON_DISPLAYABLE,
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.pTileInfo = &tile_info,
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.tileIndex = -1,
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};
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ADDR_COMPUTE_SURFACE_INFO_OUTPUT out = {
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.size = sizeof(out),
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};
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addr_check(AddrComputeSurfaceInfo(hlib, &in, &out));
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*tile_width = out.pitchAlign;
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*tile_height = out.heightAlign;
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legacy_info->tile_mode_index = out.tileIndex;
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assert(out.depthAlign == 1);
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assert(out.tileMode == mode);
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}
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assert(*tile_width);
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assert(*tile_height);
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}
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static unsigned
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addr_from_coord(ADDR_HANDLE hlib, unsigned gfx_version, legacy_tile_info *legacy_info,
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unsigned bpp, unsigned swizzle_mode, unsigned x, unsigned y)
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{
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if (gfx_version >= 12) {
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ADDR3_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT in = {
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.size = sizeof(in),
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.x = x,
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.y = y,
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.swizzleMode = swizzle_mode,
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.flags = {{0}},
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.resourceType = ADDR_RSRC_TEX_2D,
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.bpp = bpp,
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.unAlignedDims = {
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.width = 4096,
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.height = 4096,
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.depth = 1,
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},
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.numMipLevels = 1,
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.numSamples = 1,
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.pitchInElement = 4096,
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};
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ADDR3_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT out = {
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.size = sizeof(out),
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};
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addr_check(Addr3ComputeSurfaceAddrFromCoord(hlib, &in, &out));
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return out.addr;
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} else if (gfx_version >= 9) {
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ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT in = {
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.size = sizeof(in),
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.x = x,
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.y = y,
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.swizzleMode = swizzle_mode,
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.flags = {
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.color = 1,
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},
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.resourceType = ADDR_RSRC_TEX_2D,
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.bpp = bpp,
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.unalignedWidth = 4096,
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.unalignedHeight = 4096,
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.numSlices = 1,
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.numMipLevels = 1,
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.numSamples = 1,
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.numFrags = 1,
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.pitchInElement = 4096,
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};
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ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT out = {
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.size = sizeof(out),
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};
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addr_check(Addr2ComputeSurfaceAddrFromCoord(hlib, &in, &out));
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return out.addr;
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} else {
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ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT in = {
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.size = sizeof(in),
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.x = x,
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.y = y,
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.bpp = bpp,
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.pitch = 4096,
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.height = 4096,
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.numSlices = 1,
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.numSamples = 1,
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.numFrags = 1,
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.tileIndex = legacy_info->tile_mode_index,
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};
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ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT out = {
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.size = sizeof(out),
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};
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addr_check(AddrComputeSurfaceAddrFromCoord(hlib, &in, &out));
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return out.addr;
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}
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}
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static void
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print_tiling_layouts(const struct amdgpu_device *dev)
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{
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unsigned gfx_version = dev->hw_ip_gfx.hw_ip_version_major;
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ADDR_HANDLE lib = addrlib_create(dev);
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static const unsigned gfx6_array_modes_2D[] = {
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ADDR_TM_LINEAR_ALIGNED,
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ADDR_TM_1D_TILED_THIN1,
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ADDR_TM_1D_TILED_THIN1 | DIPLAYABLE,
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#if 0 /* Layouts with XORs are commented out for now. */
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ADDR_TM_2D_TILED_THIN1,
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ADDR_TM_2D_TILED_THIN1 | DIPLAYABLE,
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ADDR_TM_PRT_TILED_THIN1,
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#endif
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/* ADDR_TM_PRT_2D_TILED_THIN1 is not supported by gfx7-8 */
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};
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/* Note: Layouts with XORs are commented out for now. */
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static const unsigned gfx9_swizzle_mode_2D[] = {
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0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, /*16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,*/
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};
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static const unsigned gfx10_swizzle_mode_2D[] = {
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0, 1, 2, 5, 6, 9, 10, /*17, 18, 21, 22, 23, 24, 25, 26, 27*/
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};
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static const unsigned gfx11_swizzle_mode_2D[] = {
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0, 2, 6, 10, /*18, 21, 22, 24, 25, 26, 27, 28, 29, 30, 31*/
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};
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static const unsigned gfx12_swizzle_modes_2D[] = {
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0, 1, 2, 3, 4
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};
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const unsigned *swizzle_modes_2D = NULL;
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unsigned num_swizzle_modes_2D = 0;
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if (gfx_version >= 12) {
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swizzle_modes_2D = gfx12_swizzle_modes_2D;
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num_swizzle_modes_2D = ARRAY_SIZE(gfx12_swizzle_modes_2D);
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} else if (gfx_version >= 11) {
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swizzle_modes_2D = gfx11_swizzle_mode_2D;
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num_swizzle_modes_2D = ARRAY_SIZE(gfx11_swizzle_mode_2D);
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} else if (gfx_version >= 10) {
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swizzle_modes_2D = gfx10_swizzle_mode_2D;
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num_swizzle_modes_2D = ARRAY_SIZE(gfx10_swizzle_mode_2D);
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} else if (gfx_version >= 9) {
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swizzle_modes_2D = gfx9_swizzle_mode_2D;
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num_swizzle_modes_2D = ARRAY_SIZE(gfx9_swizzle_mode_2D);
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} else {
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swizzle_modes_2D = gfx6_array_modes_2D;
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num_swizzle_modes_2D = ARRAY_SIZE(gfx6_array_modes_2D);
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}
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for (unsigned bpp = 8; bpp <= 64; bpp *= 2) {
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for (unsigned sw_index = 0; sw_index < num_swizzle_modes_2D; sw_index++) {
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unsigned swizzle_mode = swizzle_modes_2D[sw_index];
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unsigned tile_width = 0, tile_height = 0;
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legacy_tile_info legacy_info = {0};
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get_tile_size(lib, gfx_version, bpp, swizzle_mode, &tile_width, &tile_height, &legacy_info);
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unsigned num_x_bits = util_logbase2(tile_width);
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unsigned num_y_bits = util_logbase2(tile_height);
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ADDR_EQUATION equation = {
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.numBits = util_logbase2(bpp / 8) + num_x_bits + num_y_bits,
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.numBitComponents = 1,
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};
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for (unsigned coord = 0; coord < 2; coord++) {
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for (unsigned bit = 0; bit < (coord ? num_y_bits : num_x_bits); bit++) {
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unsigned x = coord == 0 ? BITFIELD_BIT(bit) : 0;
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unsigned y = coord == 1 ? BITFIELD_BIT(bit) : 0;
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unsigned addr = addr_from_coord(lib, gfx_version, &legacy_info, bpp, swizzle_mode, x, y);
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unsigned addr_pos = u_bit_scan(&addr);
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assert(addr == 0 && "layout with XORs are unhandled");
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#if 0
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printf("bpp %u, sw %u, %cbit %u (%u,%u), pos %u\n", bpp, swizzle_mode, "xy"[coord], bit, x, y, bit_pos);
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#endif
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assert(addr_pos < equation.numBits);
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assert(!equation.addr[addr_pos].valid);
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equation.addr[addr_pos].valid = true;
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equation.addr[addr_pos].channel = coord;
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equation.addr[addr_pos].index = bit;
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}
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}
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/* Print the equation. */
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printf("%s, bpe %u, sw %2u, {", dev->name, bpp / 8, swizzle_mode);
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for (unsigned bit = 0; bit < equation.numBits; bit++) {
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for (unsigned comp = 0; comp < equation.numBitComponents; comp++) {
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ADDR_CHANNEL_SETTING swizzle = equation.comps[comp][bit];
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if (swizzle.valid) {
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printf("%c%u", "XYZS"[swizzle.channel], swizzle.index);
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} else {
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printf(" 0");
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}
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}
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if (bit < equation.numBits - 1)
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printf(", ");
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}
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printf("}\n");
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}
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}
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AddrDestroy(lib);
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}
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int
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main(int argc, char **argv)
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{
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for (int d = 0; d < num_amdgpu_devices; d++) {
|
||||
const struct amdgpu_device *dev = &amdgpu_devices[d];
|
||||
|
||||
print_tiling_layouts(dev);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
Loading…
Add table
Reference in a new issue