Anuj Phogat
6c14b66e40
meta: Use is_power_of_two() helper function
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Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2015-06-15 09:07:28 -07:00
Anuj Phogat
278460279b
i965: Check for miptree pitch alignment before using intel_miptree_map_movntdqa()
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We have an assert() in intel_miptree_map_movntdqa() which expects
the pitch to be 16 byte aligned.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2015-06-15 09:07:28 -07:00
Anuj Phogat
84d27c32d2
i965: Remove break after return
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Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2015-06-15 09:07:28 -07:00
Jürgen Rühle
2e42deb29c
nv50/ir: OP_JOIN is a flow instruction
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OP_JOIN instructions are assumed to be flow instructions and mercilessly
casted to FlowInstruction.
This patch fixes an instance where an OP_JOIN is created as a plain
instruction. This can cause crashes in the ir printer.
[imirkin: add ->fixed = 1]
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-06-15 11:46:32 -04:00
Emil Velikov
061c9bc204
docs: add news item and link release notes for mesa 10.6.0
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Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2015-06-15 08:57:56 +01:00
Emil Velikov
f9e0441328
docs: Add sha256sums for the 10.6.0 release
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Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit 5d327b3735 )
2015-06-15 08:57:55 +01:00
Emil Velikov
311abe7fbd
docs: Update 10.6.0 release notes
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Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit 3b9cde5c81 )
2015-06-15 08:57:55 +01:00
Chia-I Wu
94ab563671
ilo: add ilo_state_raster_{line,poly}_stipple
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Initialize hardware stipple states on bound instead of on emission.
2015-06-15 15:06:11 +08:00
Chia-I Wu
7cb853d52a
ilo: add ilo_state_sample_pattern
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Move sample pattern initialization from ilo_render to
ilo_state_sample_pattern.
2015-06-15 15:06:11 +08:00
Chia-I Wu
8f37e8e64f
ilo: add 3DSTATE_AA_LINE_PARAMETERS to ilo_state_raster
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Utilize ilo_state_raster to avoid redundant state change.
2015-06-15 15:06:11 +08:00
Marek Olšák
b0a2280e45
gallium/util: add util_last_bit64
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This will be needed by radeonsi.
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-06-14 20:17:29 +02:00
Marek Olšák
2489054f66
glsl: fix "tesselation" typo
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Trivial.
2015-06-14 20:17:29 +02:00
Marek Olšák
790510808e
r600g: handle TGSI input/output array declarations correctly
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Most of this code could be removed if r600g used tgsi_shader_info.
2015-06-14 20:17:29 +02:00
Chia-I Wu
117926debb
ilo: merge ilo_state_3d*.[ch] to ilo_state.[ch]
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With most code replaced to ilo_state_*, what was left did not belong there
anymore.
2015-06-15 01:23:23 +08:00
Chia-I Wu
54e0a8ed5d
ilo: add ilo_state_ps to ilo_shader_cso
2015-06-15 01:22:13 +08:00
Chia-I Wu
30fcb31c9b
ilo: add ilo_state_{vs,hs,ds,gs} to ilo_shader_cso
2015-06-15 01:07:10 +08:00
Chia-I Wu
da6e45fcbc
ilo: embed ilo_state_sbe in ilo_shader
2015-06-15 01:07:10 +08:00
Chia-I Wu
5a52627c4f
ilo: embed ilo_state_vf in ilo_ve_state
2015-06-15 01:07:09 +08:00
Chia-I Wu
9bfa987fb0
ilo: embed ilo_state_urb in ilo_state_vector
2015-06-15 01:07:09 +08:00
Chia-I Wu
eaf2c73899
ilo: embed ilo_state_sol in ilo_shader
2015-06-15 01:07:09 +08:00
Chia-I Wu
960ca7d5e3
ilo: embed ilo_state_cc in ilo_blend_state
2015-06-15 01:07:09 +08:00
Chia-I Wu
402e155cd3
ilo: embed ilo_state_raster in ilo_rasterizer_state
2015-06-15 01:07:09 +08:00
Chia-I Wu
ded7d412d0
ilo: embed ilo_state_viewport in ilo_viewport_state
2015-06-15 01:06:45 +08:00
Chia-I Wu
4b5c0a8341
ilo: replace ilo_sampler_cso with ilo_state_sampler
2015-06-15 01:06:45 +08:00
Chia-I Wu
745ef2c07b
ilo: replace ilo_view_surface with ilo_state_surface
2015-06-15 01:06:45 +08:00
Chia-I Wu
c10c1ac0cf
ilo: replace ilo_zs_surface with ilo_state_zs
2015-06-15 01:06:44 +08:00
Chia-I Wu
6dad848d1a
ilo: add ilo_state_ps
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We want to make ilo_shader_cso a union of ilo_state_{vs,hs,ds,gs,ps}.
2015-06-15 01:06:44 +08:00
Chia-I Wu
df9f846ac6
ilo: add ilo_state_{vs,hs,ds,gs}
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We want to make ilo_shader_cso a union of ilo_state_{vs,hs,ds,gs} and ps
payload.
2015-06-15 01:06:44 +08:00
Chia-I Wu
a0bb1c2d17
ilo: add ilo_state_sbe
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We want to replace ilo_kernel_routing with ilo_state_sbe.
2015-06-15 01:06:44 +08:00
Chia-I Wu
1ccab943b6
ilo: add ilo_state_vf
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We want to replace ilo_ve_state with ilo_state_vf.
2015-06-15 01:06:44 +08:00
Chia-I Wu
9c77ebef24
ilo: add ilo_state_urb
2015-06-15 01:06:44 +08:00
Chia-I Wu
3ff40be0ee
ilo: add ilo_state_sol
2015-06-15 01:06:44 +08:00
Chia-I Wu
62bb643718
ilo: add ilo_state_cc
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We want to replace ilo_dsa_state and ilo_blend_state with ilo_state_cc.
2015-06-15 01:06:44 +08:00
Chia-I Wu
6be8b6053d
ilo: add ilo_state_raster
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We want to replace ilo_rasterizer_state with ilo_state_raster.
2015-06-15 01:06:44 +08:00
Chia-I Wu
4fa7ed99a1
ilo: add ilo_state_viewport
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We want to replace ilo_viewport_cso and ilo_scissor_state with
ilo_state_viewport.
2015-06-14 23:00:04 +08:00
Chia-I Wu
61fea171af
ilo: add ilo_state_sampler
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We want to replace ilo_sampler_cso with ilo_state_sampler.
2015-06-14 23:00:04 +08:00
Chia-I Wu
f5f2007322
ilo: add ilo_state_surface
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We want to replace ilo_view_surface with ilo_state_surface.
2015-06-14 23:00:04 +08:00
Chia-I Wu
b91250a56b
ilo: add ilo_state_zs
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We want to replace ilo_zs_surface with ilo_state_zs. One noteworthy
difference is that ilo_state_zs always aligns level 0 to 8x4 when HiZ is
enabled. HiZ will not be enabled for 1D surfaces as a result.
2015-06-14 23:00:03 +08:00
Chia-I Wu
9af1fc590d
ilo: update genhw headers
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Generate these new enums
enum gen_reorder_mode;
enum gen_clip_mode;
enum gen_front_winding;
enum gen_fill_mode;
enum gen_cull_mode;
enum gen_pixel_location;
enum gen_sample_count;
enum gen_inputattr_select;
enum gen_msrast_mode;
enum gen_prefilter_op;
Correct the type of GEN6_SAMPLER_DW0_BASE_LOD. Rename gen_logicop_function,
gen_sampler_mip_filter, gen_sampler_map_filter, gen_sampler_aniso_ratio, and
others.
2015-06-14 15:43:20 +08:00
Chia-I Wu
9cb0df4b50
ilo: add ilo_image_disable_aux()
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When aux bo allocation fails, ilo_image_disable_aux() should be called to
disable aux buffer.
2015-06-14 15:43:20 +08:00
Chia-I Wu
f0de65cbc2
ilo: add array_size and level_count to ilo_image
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We will use them for bound checking.
2015-06-14 15:43:20 +08:00
Chia-I Wu
f9d2bbe967
ilo: add pipe_texture_target to ilo_image
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Save the target in ilo_image instead of passing it around.
2015-06-14 15:43:20 +08:00
Chia-I Wu
9da9cf729f
ilo: fix "Render Cache Read Write Mode"
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It needs be set to R/W only when using certain messages via DP render cache.
Since we only use RT wrties with the render cache, we never need to set it.
2015-06-14 15:43:20 +08:00
Chia-I Wu
1885ac4908
ilo: avoid resource owning in core
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It is up to the users whether to reference count the BOs or not.
2015-06-14 15:43:20 +08:00
Chia-I Wu
ab7229b9b6
ilo: assert core objects are zero-initialized
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Core objects are usually embedded inside calloc()'ed objects and we expect
them to be zero-initialized.
2015-06-14 15:43:20 +08:00
Tom Stellard
4d35eef326
radeon/llvm: Handle LLVM backend rename from R600 to AMDGPU
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Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2015-06-12 21:02:00 -07:00
Tom Stellard
3e74122337
gallivm: Only build lp_profile() body when PROFILE is defined
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The only use of lp_profile() is wrapped in #if defined(PROFILE),
so there is no reason to build it unless this macro is defined.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2015-06-12 21:02:00 -07:00
Timothy Arceri
faf7670ee8
glsl: fix compile error message
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Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2015-06-13 12:21:26 +10:00
Kristian Høgsberg Kristensen
fa8a07748d
vk: Compute CS exec mask and thread width max in pipeline
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We compute the right mask and thread width max parameters as part of
pipeline creation and set them accordingly at vkCmdDispatch() and
vkCmdDispatchIndirect() time. These parameters depend only on the local
group size and the dispatch width of the program so we can figure this
out at pipeline create time.
2015-06-12 18:21:50 -07:00
Kristian Høgsberg Kristensen
c103c4990c
vk: Set binding table layout for CS
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We weren't setting the binding table layout for the backend compiler.
2015-06-12 18:21:49 -07:00