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ilo: fix "Render Cache Read Write Mode"

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It needs be set to R/W only when using certain messages via DP render cache.
Since we only use RT wrties with the render cache, we never need to set it.
This commit is contained in:
Chia-I Wu 2015-05-15 10:39:05 +08:00
parent 1885ac4908
commit 9da9cf729f
5 changed files with 12 additions and 28 deletions
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2
src/gallium/drivers/ilo/core/ilo_builder_3d_top.h
View file

@ -1711,7 +1711,7 @@ gen6_so_SURFACE_STATE(struct ilo_builder *builder,
}
ilo_gpe_init_view_surface_for_buffer(builder->dev, buf, bo_offset,
so->buffer_size, struct_size, elem_format, false, true, &surf);
so->buffer_size, struct_size, elem_format, false, &surf);
return gen6_SURFACE_STATE(builder, &surf, false);
}

2
src/gallium/drivers/ilo/core/ilo_state_3d.h
View file

@ -380,7 +380,7 @@ ilo_gpe_init_view_surface_for_buffer(const struct ilo_dev *dev,
unsigned offset, unsigned size,
unsigned struct_size,
enum pipe_format elem_format,
bool is_rt, bool render_cache_rw,
bool is_rt,
struct ilo_view_surface *surf);
void

22
src/gallium/drivers/ilo/core/ilo_state_3d_top.c
View file

@ -469,8 +469,7 @@ view_init_for_buffer_gen6(const struct ilo_dev *dev,
unsigned offset, unsigned size,
unsigned struct_size,
enum pipe_format elem_format,
bool is_rt, bool render_cache_rw,
struct ilo_view_surface *surf)
bool is_rt, struct ilo_view_surface *surf)
{
const int elem_size = util_format_get_blocksize(elem_format);
int width, height, depth, pitch;
@ -539,8 +538,6 @@ view_init_for_buffer_gen6(const struct ilo_dev *dev,
dw[0] = GEN6_SURFTYPE_BUFFER << GEN6_SURFACE_DW0_TYPE__SHIFT |
surface_format << GEN6_SURFACE_DW0_FORMAT__SHIFT;
if (render_cache_rw)
dw[0] |= GEN6_SURFACE_DW0_RENDER_CACHE_RW;
dw[1] = offset;
@ -691,9 +688,6 @@ view_init_for_image_gen6(const struct ilo_dev *dev,
GEN6_SURFACE_DW0_CUBE_FACE_ENABLES__MASK;
}
if (is_rt)
dw[0] |= GEN6_SURFACE_DW0_RENDER_CACHE_RW;
dw[1] = 0;
dw[2] = (height - 1) << GEN6_SURFACE_DW2_HEIGHT__SHIFT |
@ -795,8 +789,7 @@ view_init_for_buffer_gen7(const struct ilo_dev *dev,
unsigned offset, unsigned size,
unsigned struct_size,
enum pipe_format elem_format,
bool is_rt, bool render_cache_rw,
struct ilo_view_surface *surf)
bool is_rt, struct ilo_view_surface *surf)
{
const bool typed = (elem_format != PIPE_FORMAT_NONE);
const bool structured = (!typed && struct_size > 1);
@ -886,8 +879,6 @@ view_init_for_buffer_gen7(const struct ilo_dev *dev,
dw[0] = surface_type << GEN7_SURFACE_DW0_TYPE__SHIFT |
surface_format << GEN7_SURFACE_DW0_FORMAT__SHIFT;
if (render_cache_rw)
dw[0] |= GEN7_SURFACE_DW0_RENDER_CACHE_RW;
if (ilo_dev_gen(dev) >= ILO_GEN(8)) {
dw[8] = offset;
@ -1117,9 +1108,6 @@ view_init_for_image_gen7(const struct ilo_dev *dev,
dw[0] |= GEN7_SURFACE_DW0_ARYSPC_FULL;
}
if (is_rt)
dw[0] |= GEN7_SURFACE_DW0_RENDER_CACHE_RW;
if (surface_type == GEN6_SURFTYPE_CUBE && !is_rt)
dw[0] |= GEN7_SURFACE_DW0_CUBE_FACE_ENABLES__MASK;
@ -1213,15 +1201,15 @@ ilo_gpe_init_view_surface_for_buffer(const struct ilo_dev *dev,
unsigned offset, unsigned size,
unsigned struct_size,
enum pipe_format elem_format,
bool is_rt, bool render_cache_rw,
bool is_rt,
struct ilo_view_surface *surf)
{
if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
view_init_for_buffer_gen7(dev, buf, offset, size,
struct_size, elem_format, is_rt, render_cache_rw, surf);
struct_size, elem_format, is_rt, surf);
} else {
view_init_for_buffer_gen6(dev, buf, offset, size,
struct_size, elem_format, is_rt, render_cache_rw, surf);
struct_size, elem_format, is_rt, surf);
}
/* do not increment reference count */

4
src/gallium/drivers/ilo/ilo_render_surface.c
View file

@ -437,7 +437,7 @@ gen6_emit_launch_grid_surface_const(struct ilo_render *r,
session->input->buffer_offset,
session->input->buffer_size,
1, PIPE_FORMAT_NONE,
false, false, &view);
false, &view);
assert(count == 1 && session->input->buffer);
surface_state[base] = gen6_SURFACE_STATE(r->builder, &view, false);
@ -488,7 +488,7 @@ gen6_emit_launch_grid_surface_global(struct ilo_render *r,
assert(bindings[i].resource->target == PIPE_BUFFER);
ilo_gpe_init_view_surface_for_buffer(r->dev, buf, 0, buf->bo_size,
1, PIPE_FORMAT_NONE, true, true, &view);
1, PIPE_FORMAT_NONE, true, &view);
surface_state[i] =
gen6_SURFACE_STATE(r->builder, &view, true);
} else {

10
src/gallium/drivers/ilo/ilo_state.c
View file

@ -112,7 +112,7 @@ finalize_cbuf_state(struct ilo_context *ilo,
ilo_buffer(cbuf->cso[i].resource),
offset, cbuf->cso[i].user_buffer_size,
util_format_get_blocksize(elem_format), elem_format,
false, false, &cbuf->cso[i].surface);
false, &cbuf->cso[i].surface);
ilo->state_vector.dirty |= ILO_DIRTY_CBUF;
}
@ -683,7 +683,7 @@ ilo_set_constant_buffer(struct pipe_context *pipe,
ilo_buffer(buf[i].buffer),
buf[i].buffer_offset, buf[i].buffer_size,
util_format_get_blocksize(elem_format), elem_format,
false, false, &cso->surface);
false, &cso->surface);
cso->user_buffer = NULL;
cso->user_buffer_size = 0;
@ -1007,7 +1007,7 @@ ilo_create_sampler_view(struct pipe_context *pipe,
ilo_gpe_init_view_surface_for_buffer(dev, ilo_buffer(res),
first_elem * elem_size, num_elems * elem_size,
elem_size, templ->format, false, false, &view->surface);
elem_size, templ->format, false, &view->surface);
}
else {
struct ilo_texture *tex = ilo_texture(res);
@ -1066,10 +1066,6 @@ ilo_create_surface(struct pipe_context *pipe,
/* relax this? */
assert(tex->base.target != PIPE_BUFFER);
/*
* classic i965 sets render_cache_rw for constant buffers and sol
* surfaces but not render buffers. Why?
*/
ilo_gpe_init_view_surface_for_image(dev,
&tex->image, tex->base.target,
templ->format, templ->u.tex.level, 1,