Commit graph

74805 commits

Author SHA1 Message Date
Matt Turner
48b4e88d3d i965: Don't mark dead instructions' sources live.
Removes dead code from glsl-mat-from-int-ctor-03.shader_test.

Reported-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-12-01 14:48:55 -08:00
Dave Airlie
0e49151dcf r600: set mega fetch count to 16 for gs copy shader
Seems like MFC should be set for this shader.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-12-02 08:25:13 +10:00
Dave Airlie
4ebcf5194d r600: increment ring index after emit vertex not before.
The docs say we should send the emit after the ring writes,
so lets do that and not have an ALU in between.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-12-02 08:25:13 +10:00
Dave Airlie
13b134a443 r600: add alu + cf nop to copy shader on r600
SB suggests we do this for r600, so lets do it,
for the copy shader.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-12-02 08:25:13 +10:00
Dave Airlie
af4013d26b r600: SMX returns CONTEXT_DONE early workaround
streamout, gs rings bug on certain r600s, requires a wait idle
before each surface sync.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: "10.6 11.0 11.1" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-12-02 08:25:00 +10:00
Dave Airlie
b63944e8b9 r600: do SQ flush ES ring rolling workaround
Need to insert a SQ_NON_EVENT when ever geometry
shaders are enabled.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: "10.6 11.0 11.1" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-12-02 08:24:32 +10:00
Samuel Pitoiset
ea33920f7e nv50,nvc0: allow to create resources other than buffers
For the compute support, we might stick buffers as surfaces. This fixes
an assertion when executing src/gallium/tests/trivial/compute.

To avoid using these "restricted" surfaces as render targets, these
assertions have been moved. Note that it's already handled for the
framebuffer thing on nvc0.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-12-01 22:55:14 +01:00
Brian Paul
f391b95105 glapi: work-around MSVC 65K string length limitation for enums.c
String literals cannot exceed 65535 characters for MSVC.  Instead of
emiting a string, emit an array of characters.

v2: fix indentation and add comment in the gl_enums.py file about this
ugliness.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2015-12-01 14:28:45 -07:00
Eric Anholt
148c2f5b17 mapi: Fix enums.c build with other build systems.
Tested with scons (by both myself and Mark Janes), Android is just copy
and paste.
2015-12-01 12:19:02 -08:00
Eric Anholt
1c0ac1976a travis: Initial import of travis instructions.
This just builds/installs our dependencies, and runs "make check".  I'm
interested in integrating more tests into it, but this seems like a pretty
easy first start.

If your personal branches of Mesa are on github, you can enable it on your
account and the repository (see
https://docs.travis-ci.com/user/for-beginners), then any pushes you do
will get their HEAD commit tested, and any pull requests to your tree will
get their merge commits tested.
2015-12-01 11:08:57 -08:00
Eric Anholt
4922a3ae52 mesa: Drop the blacklisting of new GL enums.
Now when people need new extensions, they can skip the entire
enum-definition process, and we can stop reviewing new extension XML for
its enum content.

This also brings in a new enum that I wanted to use in enum_strings.cpp
for testing the code generator.

v2: Drop comment about disabled GL_1PASS_EXT test.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2015-12-01 10:24:42 -08:00
Eric Anholt
b65e44f55d mesa: Use a 32-bit offset for the enums.c string offset table.
With GLES 3.1, GL 4.5, and many new vendor extensions about to get their
enums added, we jump up to 85k of table.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2015-12-01 10:24:41 -08:00
Eric Anholt
c75cfe1c8a mesa: Prefer newer names to older ones among names present in core.
Sometimes GL likes to rename an old enum when it grows a more general
purpose, and we should prefer the new name.  Changes from this:

GL_POINT/LINE_SIZE_* (1.1) -> GL_SMOOTH_POINT/LINE_SIZE_* (1.2)
GL_FOG_COORDINATE_* (1.4) -> GL_FOG_COORD_* (1.5)
GL_SOURCE[012]_RGB/ALPHA (1.3) -> GL_SRC0_RGB (1.5)
GL_COPY_READ/WRITE_BUFFER (3.1) -> GL_COPY_READ_BUFFER_BINDING (4.2)

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2015-12-01 10:24:38 -08:00
Eric Anholt
710762b64a mesa: Drop bitfield "enums" from the enum-to-string table.
Asking the table for bitfield names doesn't make any sense.  For 0x10, do
you want GL_GLYPH_HORIZONTAL_BEARING_ADVANCE_BIT_NV or
GL_COLOR_BUFFER_BIT4_QCOM or GL_POLYGON_STIPPLE_BIT or
GL_SHADER_GLOBAL_ACCESS_BARRIER_BIT_NV?  Giving a useful answer would
depend on a whole lot of context.

This also fixes a bad enum table entry, where we chose GL_HINT_BIT instead
of GL_ABGR_EXT for 0x8000, so we can now fix its entry in the enum_strings
test.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2015-12-01 10:24:36 -08:00
Eric Anholt
cbabf5f9dc mesa: Switch to using the Khronos registry for generating enums.
I've used a bunch of python code to cut out new enums so that the two
generated files can be diffed.  I'll remove all that hardcoding in the
following commits.  All remaining differences between the generated code:

- GL_TEXTURE_BUFFER_FORMAT didn't appear in GL3 when TBOs got merged to
  core, so it now gets an _ARB suffix instead.

- Blacklisting can't keep EXT_sso's GL_ACTIVE_PROGRAM_EXT from becoming
  GL_ACTIVE_PROGRAM -- in our hash table, GL_ACTIVE_PROGRAM_EXT points at
  the GLES2 enum's value (aka GL_CURRENT_PROGRAM).  By not blacklisting
  the core name, we get both enums translated.

- GL_DRAW_FRAMEBUFFER_BINDING and GL_FRAMEBUFFER_BINDING both appeared in
  GL3 as synonyms, and the new code happens to choose
  GL_FRAMEBUFFER_BINDING instead.

- GL_TEXTURE_COMPONENTS and GL_TEXTURE_INTERNAL_FORMAT both appear in 1.1,
  and the new code chooses GL_TEXTURE_INTERNAL_FORMAT instead (which seems
  better, to me)

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2015-12-01 10:24:34 -08:00
Eric Anholt
f72923aaea mesa: Remove the python mode bits from gl_enums.py.
emacs whines at me every time I open the file about these unsafe
variables, and the file was reformatted from 8 space to 4 space long ago.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2015-12-01 10:24:31 -08:00
Eric Anholt
741f642a6f mesa: Drop apparently typoed GL_ALL_CLIENT_ATTRIB_BITS.
GL_ALL_ATTRIB_BITS is a thing, and GL_CLIENT_ALL_ATTRIB_BITS, but I don't
see GL_ALL_CLIENT_ATTRIB_BITS in my grepping of khronos XML, GL extension
specs, GL 1.1, GL 2.2, and GL 4.4.

Reviewed-by: Brian Paul <brianp@vmware.com>
2015-12-01 10:24:22 -08:00
Eric Anholt
5cb9dc45c7 mesa: Drop enums that had been removed in later revs of specs.
Mesa hasn't been using these enums and the finalized specs don't reference
them, so losing them from our generated enum-to-string code should be
fine.  Reduces diffs to generating from Khronos XML, which has these enums
noted defined but commented out from any consumers.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2015-12-01 10:24:18 -08:00
Eric Anholt
5a7e5d8bb6 mesa: Fix a typo in AMD_performance_monitor enum.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2015-12-01 10:24:16 -08:00
Eric Anholt
bfc64b9688 mesa: Fix enum definition of CULL_VERTEX_EYE/OBJECT_POSITION
In converting to using the Khronos XML, I found that our XML had these two
swapped, and the text spec agreed.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2015-12-01 10:24:15 -08:00
Eric Anholt
76ec0b9038 mesa: Add a copy of the Khronos gl.xml (SVN #31705).
The intention here is to keep a pristine copy of the upstream gl.xml that
can be updated at any time with a new version, and use that to generate
Mesa code from instead of our private XML.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2015-12-01 10:24:13 -08:00
Eric Anholt
edc8850436 mesa: Cut enum_strings.cpp test down to a few hand-chosen enums.
The previous contents appeared to be the output of some form of code
generation for all enums, with a few entries hand-edited to deal with
oddness.  The downside to this was that when an enum gets promoted from
vendor to _EXT or _EXT to _ARB or _ARB to core, make check starts failing
even when the commiter has done nothing wrong.  Instead of black-box
testing the code generation, pick a few enums that intentionally poke the
interesting cases of code generation.

People editing the code generator should be diffing the generated code
anyway.  This should catch when they fail to do so, without throwing false
negatives when people update the GL XML.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2015-12-01 10:24:02 -08:00
Tom Stellard
9adbb9e713 clover: Handle NULL devices returned by pipe_loader_probe() v2
When probing for devices, clover will call pipe_loader_probe() twice.
The first time to retrieve the number of devices, and then second time
to retrieve the device structures.

We currently assume that the return value of both calls will be the
same, but this will not be the case if a device happens to disappear
between the two calls.

When a device disappears, the pipe_loader_probe() will add a NULL
device to the device list, so we need to handle this.

v2:
  - Keep range for loop

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Acked-by: Emil Velikov <emil.l.velikov@gmail.com>

CC: <mesa-stable@lists.freedesktop.org>
2015-12-01 16:00:54 +00:00
Jonathan Gray
99cd600835 automake: fix some occurrences of hardcoded -ldl and -lpthread
Correct some occurrences of -ldl and -lpthread to use
$(DLOPEN_LIBS) and $(PTHREAD_LIBS) respectively.

Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2015-12-01 16:53:40 +00:00
Iago Toral Quiroga
241f15ac80 glsl/lower_ubo_reference: split struct copies into element copies
Improves register pressure, since otherwise we end up emitting
loads for all the elements in the RHS and them emitting
stores for all elements in the LHS.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2015-12-01 13:30:42 +01:00
Iago Toral Quiroga
867c436ca8 glsl/lower_ubo_reference: split array copies into element copies
Improves register pressure, since otherwise we end up emitting
loads for all the elements in the RHS and them emitting
stores for all elements in the LHS.

v2:
  - Mark progress properly. This also fixes some instances where the added
    nodes with individual element copies where not being lowered, which is
    expected behavior as explained in the documentation for
    visit_list_elements.
  - Only need to do this if the RHS is a buffer-backed variable.
  - We can also have arrays inside structs. A later patch will make it so
    we also split struct copies and end up with multiple
    ir_dereference_record assignments, so make sure that if any of these
    is an array copy, we also split it.

Fixes the following piglit tests:
tests/spec/arb_shader_storage_buffer_object/execution/large-field-copy.shader_test
tests/spec/arb_shader_storage_buffer_object/linker/copy-large-array.shader_test

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2015-12-01 13:29:57 +01:00
Julien Isorce
e483cba9f5 st/va: also retrieve reference frames info for h264
Other hardwares than AMD require to parse:
VAPictureParameterBufferH264.ReferenceFrames[16]

Signed-off-by: Julien Isorce <j.isorce@samsung.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2015-12-01 08:21:37 +00:00
Julien Isorce
b4fb6d7616 st/va: delay decoder creation until max_references is known
In general max_references cannot be based on num_render_targets.

This patch allows to allocate buffers with an accurate size.
I.e. no more than necessary. For other codecs it is a fixed
value 2.

This is similar behaviour as vaapi/vdpau-driver.

For now HEVC case defaults to num_render_targets as before.
But it could also benefits this change by setting a more
accurate max_references number in handlePictureParameterBuffer.

Signed-off-by: Julien Isorce <j.isorce@samsung.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2015-12-01 08:21:20 +00:00
Iago Toral Quiroga
750393ff7d glsl/dead_builin_varyings: Fix gl_FragData array lowering
The current implementation looks for array dereferences on gl_FragData and
immediately proceeds to lower them, however this is not enough because we
can have array access on vector variables too, like in this code:

out vec4 color;
void main()
{
   int i;
   for (i = 0; i < 4; i++)
      color[i] = 1.0;
}

Fix it by making sure that the actual variable being dereferenced is an array.

Fixes a crash in:
spec/arb_gpu_shader_fp64/execution/built-in-functions/fs-ldexp-dvec4.shader_test

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2015-12-01 08:30:52 +01:00
Dave Airlie
4f34722575 r600: workaround empty geom shader.
We need to emit at least one cut/emit in every
geometry shader, the easiest workaround it to
stick a single CUT at the top of each geom shader.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: "10.6 11.0 11.1" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-12-01 12:58:43 +10:00
Dave Airlie
04efcc6c7a r600: rv670 use at least 16es/gs threads
This is specified in the docs for rv670 to work properly.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: "10.6 11.0 11.1" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-12-01 12:58:34 +10:00
Dave Airlie
8168dfdd4e r600: geometry shader gsvs itemsize workaround
On some chips the GSVS itemsize needs to be aligned to a cacheline size.

This only applies to some of the r600 family chips.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: "10.6 11.0 11.1" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-12-01 12:57:55 +10:00
Gregory Hainaut
2ab9cd0c4d glsl: don't sort varying in separate shader mode
This fixes an issue where the addition of the FLAT qualifier in
varying_matches::record() can break the expected varying order.

It also avoids a future issue with the relaxing of interpolation
qualifier matching constraints in GLSL 4.50.

V2: (by Timothy Arceri)
* reworked comment slightly

Signed-off-by: Gregory Hainaut <gregory.hainaut@gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2015-12-01 12:46:37 +11:00
Gregory Hainaut
8117f46f49 glsl: don't dead code remove SSO varyings marked as active
GL_ARB_separate_shader_objects allow matching by name variable or block
interface. Input varyings can't be removed because it is will impact the
location assignment.

This fixes the bug 79783 and likely any application that uses
GL_ARB_separate_shader_objects extension.

V2 (by Timothy Arceri):
* simplify now that builtins are not set as always active

Signed-off-by: Gregory Hainaut <gregory.hainaut@gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
https://bugs.freedesktop.org/show_bug.cgi?id=79783
2015-12-01 12:46:32 +11:00
Gregory Hainaut
618612f867 glsl: add always_active_io attribute to ir_variable
The value will be set in separate-shader program when an input/output
must remains active. e.g. when deadcode removal isn't allowed because
it will create interface location/name-matching mismatch.

v3:
* Rename the attribute
* Use ir_variable directly instead of ir_variable_refcount_visitor
* Move the foreach IR code in the linker file

v4:
* Fix variable name in assert

v5 (by Timothy Arceri):
* Rename functions and reword comments
* Don't set always active on builtins

Signed-off-by: Gregory Hainaut <gregory.hainaut@gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2015-12-01 12:46:26 +11:00
Timothy Arceri
76c09c1792 glsl: copy how_declared when lowering interface blocks
Cc: Gregory Hainaut <gregory.hainaut@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2015-12-01 12:45:07 +11:00
Timothy Arceri
12ba6cfba7 glsl: optimise inputs/outputs with explicit locations
This change allows used defined inputs/outputs with explicit locations
to be removed if they are detected to not be used between shaders
at link time.

To enable this we change the is_unmatched_generic_inout field to be
flagged when we have a user defined varying. Previously
explicit_location was assumed to be set only in builtins however SSO
allows the user to set an explicit location.

We then add a function to match explicit locations between shaders.

V2: call match_explicit_outputs_to_inputs() after
is_unmatched_generic_inout has been initialised.

Cc: Gregory Hainaut <gregory.hainaut@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2015-12-01 12:45:03 +11:00
Dave Airlie
4d64459a92 r600/shader: split address get out to a function.
This will be used in the tess shaders.

Reviewed-by: Oded Gabbay <oded.gabbay@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-12-01 08:10:21 +10:00
Marta Lofstedt
44944a66ce doc: Set GL_OES_geometry_shader as started
Signed-off-by: Marta Lofstedt <marta.lofstedt@linux.intel.com>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
2015-11-30 10:47:21 +01:00
Marta Lofstedt
1d5b88e33b gles2: Update gl2ext.h to revision: 32120
This is needed to be able to implement the accepted OES
extensions.

Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Marta Lofstedt <marta.lofstedt@linux.intel.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-11-30 10:46:15 +01:00
Julien Isorce
10c14919c8 vl/buffers: fixes vl_video_buffer_formats for RGBX
Fixes: 42a5e143a8 "vl/buffers: add RGBX and BGRX to the supported formats"
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Julien Isorce <j.isorce@samsung.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2015-11-30 09:02:29 +00:00
Samuel Iglesias Gonsálvez
a348fe89af i965/fs: remove unused fs_reg offset
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
2015-11-30 10:00:40 +01:00
Kenneth Graunke
83dedb6354 i965: Add src/dst interference for certain instructions with hazards.
When working on tessellation shaders, I created some vec4 virtual
opcodes for creating message headers through a sequence like:

   mov(8) g7<1>UD      0x00000000UD    { align1 WE_all 1Q compacted };
   mov(1) g7.5<1>UD    0x00000100UD    { align1 WE_all };
   mov(1) g7<1>UD      g0<0,1,0>UD     { align1 WE_all compacted };
   mov(1) g7.3<1>UD    g8<0,1,0>UD     { align1 WE_all };

This is done in the generator since the vec4 backend can't handle align1
regioning.  From the visitor's point of view, this is a single opcode:

   hs_set_output_urb_offsets vgrf7.0:UD, 1U, vgrf8.xxxx:UD

Normally, there's no hazard between sources and destinations - an
instruction (naturally) reads its sources, then writes the result to the
destination.  However, when the virtual instruction generates multiple
hardware instructions, we can get into trouble.

In the above example, if the register allocator assigned vgrf7 and vgrf8
to the same hardware register, then we'd clobber the source with 0 in
the first instruction, and read back the wrong value in the last one.

It occured to me that this is exactly the same problem we have with
SIMD16 instructions that use W/UW or B/UB types with 0 stride.  The
hardware implicitly decodes them as two SIMD8 instructions, and with
the overlapping regions, the first would clobber the second.

Previously, we handled that by incrementing the live range end IP by 1,
which works, but is excessive: the next instruction doesn't actually
care about that.  It might also be the end of control flow.  This might
keep values alive too long.  What we really want is to say "my source
and destinations interfere".

This patch creates new infrastructure for doing just that, and teaches
the register allocator to add interference when there's a hazard.  For
my vec4 case, we can determine this by switching on opcodes.  For the
SIMD16 case, we just move the existing code there.

I audited our existing virtual opcodes that generate multiple
instructions; I believe FS_OPCODE_PACK_HALF_2x16_SPLIT needs this
treatment as well, but no others.

v2: Rebased by mattst88.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-11-30 00:34:07 -08:00
Kenneth Graunke
1ac1581f38 i965: Fix JIP to properly skip over unrelated control flow.
We've apparently always been botching JIP for sequences such as:

   do
       cmp.f0.0 ...
       (+f0.0) break
       ...
       if
          ...
       else
          ...
       endif
       ...
   while

Normally, UIP is supposed to point to the final destination of the jump,
while in nested control flow, JIP is supposed to point to the end of the
current nesting level.  It essentially bounces out of the current nested
control flow, to an instruction that has a JIP which bounces out another
level, and so on.

In the above example, when setting JIP for the BREAK, we call
brw_find_next_block_end(), which begins a search after the BREAK for the
next ENDIF, ELSE, WHILE, or HALT.  It ignores the IF and finds the ELSE,
setting JIP there.

This makes no sense at all.  The break is supposed to skip over the
whole if/else/endif block entirely.  They have a sibling relationship,
not a nesting relationship.

This patch fixes brw_find_next_block_end() to track depth as it does
its search, and ignore anything not at depth 0.  So when it sees the
IF, it ignores everything until after the ENDIF.  That way, it finds
the end of the right block.

I noticed this while reading some assembly code.  We believe jumping
earlier is harmless, but makes the EU walk through a bunch of disabled
instructions for no reason.  I noticed that GLBenchmark Manhattan had
a shader that contained a BREAK with a bogus JIP, but didn't measure
any performance improvement (it's likely miniscule, if there is any).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2015-11-30 00:27:16 -08:00
Dave Airlie
d72299c531 r600: move per-type settings into a switch statement
This will allow adding tess stuff much cleaner later.

Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-11-30 11:08:00 +10:00
Dave Airlie
58e0122d86 r600: split out common alu_writes pattern.
This just splits out a common pattern into an inline function
to make things cleaner to read.

Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-11-30 11:07:18 +10:00
Dave Airlie
26332ef797 r600/llvm: fix r600/llvm build
Reported on irc by gryffus

Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-11-30 11:05:42 +10:00
Dave Airlie
9eff9f6134 r600: fixes for register definitions.
Forgot to add these.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-11-30 09:35:37 +10:00
Dave Airlie
c2e701c7ca r600: add missing register to initial state
We really should initialise HS/LS_2 and SQ_LDS_ALLOC exists
on all evergreen not just cayman, so we should initialise
it as well.

Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-11-30 09:14:16 +10:00
Dave Airlie
bcdc748fe2 r600: define registers required for tessellation
This adds the defines for a bunch of registers and shader
values that are required to implement tessellation.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-11-30 09:14:16 +10:00