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Kenneth Graunke 83dedb6354 i965: Add src/dst interference for certain instructions with hazards.
When working on tessellation shaders, I created some vec4 virtual
opcodes for creating message headers through a sequence like:

   mov(8) g7<1>UD      0x00000000UD    { align1 WE_all 1Q compacted };
   mov(1) g7.5<1>UD    0x00000100UD    { align1 WE_all };
   mov(1) g7<1>UD      g0<0,1,0>UD     { align1 WE_all compacted };
   mov(1) g7.3<1>UD    g8<0,1,0>UD     { align1 WE_all };

This is done in the generator since the vec4 backend can't handle align1
regioning.  From the visitor's point of view, this is a single opcode:

   hs_set_output_urb_offsets vgrf7.0:UD, 1U, vgrf8.xxxx:UD

Normally, there's no hazard between sources and destinations - an
instruction (naturally) reads its sources, then writes the result to the
destination.  However, when the virtual instruction generates multiple
hardware instructions, we can get into trouble.

In the above example, if the register allocator assigned vgrf7 and vgrf8
to the same hardware register, then we'd clobber the source with 0 in
the first instruction, and read back the wrong value in the last one.

It occured to me that this is exactly the same problem we have with
SIMD16 instructions that use W/UW or B/UB types with 0 stride.  The
hardware implicitly decodes them as two SIMD8 instructions, and with
the overlapping regions, the first would clobber the second.

Previously, we handled that by incrementing the live range end IP by 1,
which works, but is excessive: the next instruction doesn't actually
care about that.  It might also be the end of control flow.  This might
keep values alive too long.  What we really want is to say "my source
and destinations interfere".

This patch creates new infrastructure for doing just that, and teaches
the register allocator to add interference when there's a hazard.  For
my vec4 case, we can determine this by switching on opcodes.  For the
SIMD16 case, we just move the existing code there.

I audited our existing virtual opcodes that generate multiple
instructions; I believe FS_OPCODE_PACK_HALF_2x16_SPLIT needs this
treatment as well, but no others.

v2: Rebased by mattst88.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-11-30 00:34:07 -08:00
bin bugzilla_mesa.sh: sort the bugs list by number 2015-07-13 20:02:09 +01:00
docs docs: Update GL3.txt to add ARB_internalformat_query2 2015-11-26 23:53:16 +01:00
doxygen doxygen: Remove doxygen_sqlite3.db with 'make clean' 2015-07-11 20:48:25 +01:00
include i965/skl: PCI ID cleanup and brand strings 2015-11-03 10:00:17 -08:00
m4 configure.ac: move AC_MSG_RESULT reporting back into the m4 macro 2015-03-24 20:49:32 +00:00
scons scons: Always define __STDC_LIMIT_MACROS. 2015-08-15 01:44:33 -07:00
src i965: Add src/dst interference for certain instructions with hazards. 2015-11-30 00:34:07 -08:00
.dir-locals.el dir-locals.el: Don't set variables for non-programming modes 2015-02-02 12:02:55 +00:00
.gitattributes Disable autocrlf for Visual Studio project files. 2008-02-28 12:34:01 +09:00
.gitignore mesa: add .mesa-install-links files to gitignore 2015-04-17 15:24:14 -04:00
Android.common.mk android: Always define __STDC_LIMIT_MACROS. 2015-09-09 15:26:46 +01:00
Android.mk egl: android: remove DRM_GRALLOC_TOP hack 2015-07-22 16:35:27 +01:00
autogen.sh autogen.sh: pass --force to autoreconf, quote ORIGDIR 2015-03-11 23:28:26 +00:00
CleanSpec.mk android: Depend on gallium_dri from EGL, instead of linking in gallium. 2015-06-09 11:38:45 -07:00
common.py common.py: Fix PEP 8 issues. 2015-03-16 22:55:08 -07:00
configure.ac configure.ac: default to disabled dri3 when --disable-dri is set 2015-11-23 12:08:04 +00:00
install-gallium-links.mk targets/radeonsi/vdpau: convert to static/shared pipe-drivers 2014-06-22 23:06:01 +01:00
install-lib-links.mk install-lib-links: remove the .install-lib-links file 2015-02-24 15:33:25 +00:00
Makefile.am automake: use static llvm for make distcheck 2015-11-20 18:07:52 +00:00
SConstruct scons: Don't use bundled C99 headers for VS 2013. 2014-05-02 22:04:46 +01:00
VERSION docs: add 11.2.0-devel release notes template, bump version 2015-11-21 14:10:08 +00:00

File: docs/README.WIN32

Last updated: 21 June 2013


Quick Start
----- -----

Windows drivers are build with SCons.  Makefiles or Visual Studio projects are
no longer shipped or supported.

Run

  scons libgl-gdi

to build gallium based GDI driver.

This will work both with MSVS or Mingw.


Windows Drivers
------- -------

At this time, only the gallium GDI driver is known to work.

Source code also exists in the tree for other drivers in
src/mesa/drivers/windows, but the status of this code is unknown.

Recipe
------

Building on windows requires several open-source packages. These are
steps that work as of this writing.

- install python 2.7
- install scons (latest)
- install mingw, flex, and bison
- install pywin32 from here: http://www.lfd.uci.edu/~gohlke/pythonlibs
  get pywin32-218.4.win-amd64-py2.7.exe
- install git
- download mesa from git
  see http://www.mesa3d.org/repository.html
- run scons

General
-------

After building, you can copy the above DLL files to a place in your
PATH such as $SystemRoot/SYSTEM32.  If you don't like putting things
in a system directory, place them in the same directory as the
executable(s).  Be careful about accidentially overwriting files of
the same name in the SYSTEM32 directory.

The DLL files are built so that the external entry points use the
stdcall calling convention.

Static LIB files are not built.  The LIB files that are built with are
the linker import files associated with the DLL files.

The si-glu sources are used to build the GLU libs.  This was done
mainly to get the better tessellator code.

If you have a Windows-related build problem or question, please post
to the mesa-dev or mesa-users list.