fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-01-02 07:20:16 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 4

r600: geometry shader gsvs itemsize workaround

Browse source 
On some chips the GSVS itemsize needs to be aligned to a cacheline size.

This only applies to some of the r600 family chips.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: "10.6 11.0 11.1" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Dave Airlie 2015-02-18 23:51:19 +00:00
parent 2ab9cd0c4d
commit 8168dfdd4e
1 changed files with 20 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

20
src/gallium/drivers/r600/r600_state.c
View file

@ -2675,6 +2675,9 @@ void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *sha
S_02881C_USE_VTX_VIEWPORT_INDX(rshader->vs_out_viewport);
}
#define RV610_GSVS_ALIGN 32
#define R600_GSVS_ALIGN 16
void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
{
struct r600_context *rctx = (struct r600_context *)ctx;
@ -2684,6 +2687,23 @@ void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *sha
unsigned gsvs_itemsize =
(cp_shader->ring_item_sizes[0] * shader->selector->gs_max_out_vertices) >> 2;
/* some r600s needs gsvs itemsize aligned to cacheline size
this was fixed in rs780 and above. */
switch (rctx->b.family) {
case CHIP_RV610:
gsvs_itemsize = align(gsvs_itemsize, RV610_GSVS_ALIGN);
break;
case CHIP_R600:
case CHIP_RV630:
case CHIP_RV670:
case CHIP_RV620:
case CHIP_RV635:
gsvs_itemsize = align(gsvs_itemsize, R600_GSVS_ALIGN);
break;
default:
break;
}
r600_init_command_buffer(cb, 64);
/* VGT_GS_MODE is written by r600_emit_shader_stages */