Commit graph

222236 commits

Author SHA1 Message Date
Michael Cheng
4510b8eb38 intel/ds: Label draw events with vertex/draw counts
Format draw and draw_indexed Perfetto events with their vertex count.
For draw_indirect and draw_indexed_indirect, include the draw count
when indirect tracing is enabled (MESA_GPU_TRACES=indirects), otherwise
fall back to the static name.

Signed-off-by: Michael Cheng <michael.cheng@intel.com>
2026-05-07 22:48:16 +00:00
Michael Cheng
6373bb0faf intel/ds: Label compute events with dispatch dimensions
Format compute Perfetto events as compute(x,y,z) using end-payload
group dimensions.

For compute_indirect, the dispatch dimensions live in GPU memory at
command record time (VkDispatchIndirectCommand). The u_trace framework
copies them into a trace-local buffer at trace flush time via the
is_indirect mechanism: indirect args are passed as u_trace_address
(GPU address + bo), and u_trace copies the pointed-to struct into
indirect_data alongside the payload. The end callback receives this
as a const uint32_t* indirect pointer, which contains the x/y/z
dispatch sizes read back from the GPU. Include these dimensions when
indirect tracing is enabled (MESA_GPU_TRACES=indirects), otherwise
fall back to the static name.

Signed-off-by: Michael Cheng <michael.cheng@intel.com>
2026-05-07 22:48:16 +00:00
Michael Cheng
1b4963e382 intel/ds: Allow CREATE_DUAL_EVENT_CALLBACK to take optional name args
Refactor CREATE_DUAL_EVENT_CALLBACK to accept optional variadic
arguments for dynamic event-name formatting in follow-up patches.

Add a small helper that formats event names only when a non-NULL format
string is provided, and keep existing call sites unchanged so behavior
is identical in this commit.

Signed-off-by: Michael Cheng <michael.cheng@intel.com>
2026-05-07 22:48:16 +00:00
Marek Olšák
c6ddfe1a3b amd: add a tool that prints tiling layouts for all shim devices
This prints the swizzle pattern for all non-XOR tiling modes.
It can be used to determine which GPUs have the same tiling.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41405>
2026-05-07 21:41:01 +00:00
Mike Blumenkrantz
45706d39ea ci: stop skipping HIC tests on lavapipe
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Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41424>
2026-05-07 19:05:52 +00:00
Valentine Burley
1ed6539a07 ci/deqp: Backport host_image_copy fix
Should help with flakiness.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41424>
2026-05-07 19:05:52 +00:00
Paulo Zanoni
439c1123b0 docs/envvars: update the ANV_DEBUG documentation
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Synchronize it with the values it actually accepts right now.

v2: Other values were added by other patches after I wrote this one.

Acked-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41277>
2026-05-07 18:59:29 +00:00
Paulo Zanoni
0e81aac260 docs/envvars: document ANV_SYS_MEM_LIMIT
This option was added by fdbdfaed01 ("anv: add ANV_SYS_MEM_LIMIT for
debugging system memory restrictions").

Acked-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41277>
2026-05-07 18:59:29 +00:00
Paulo Zanoni
cf7ada8475 docs/envvars: remove ANV_SPARSE and ANV_SPARSE_USE_TRTT
These options were replaced by ANV_DEBUG=no-sparse and
ANV_DEBUG=sparse-trtt in April of 2025, by 789f13359a ("anv:
consolidate environment variables"). The ANV_DEBUG versions are
already documented.

Acked-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41277>
2026-05-07 18:59:28 +00:00
Samuel Pitoiset
4dc4012c4c radv: fix an assertion with RADV_DEBUG=fullsync on GFX11+
This can only happen with RADV_DEBUG=fullsync which literally flushes
all caches, but INV_ICACHE is invalid with RELEASE_MEM apparently.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41396>
2026-05-07 17:47:25 +00:00
Samuel Pitoiset
470897f946 radv: allow DGC+multiview by default
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It's now allowed in Vulkan.

Fixes: e47d584fed ("radv: re-introduce DGC+multiview support and enable it for vkd3d-proton only")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41395>
2026-05-07 17:08:22 +00:00
Skyth
ce4e54f7a0 spirv2dxil: Replace UAV_FENCE_THREAD_GROUP usage with UAV_FENCE_GLOBAL.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41425>
2026-05-07 16:51:25 +00:00
Tapani Pälli
c540405ca3 anv: use INTEL_NEEDS_WA_14025112257 define for workaround
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41281>
2026-05-07 16:20:29 +00:00
Tapani Pälli
c6f503bed6 iris: use INTEL_NEEDS_WA_14025112257 define for workaround
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41281>
2026-05-07 16:20:29 +00:00
Tapani Pälli
c381b4fdd4 intel/dev: update mesa_defs.json from workaround database
This removes 18042479026 as we don't utilize BRW_AOP_MOV in compiler
and adds missing xe2 entries for 14025112257.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41281>
2026-05-07 16:20:29 +00:00
Lionel Landwerlin
62b890046f anv: remove old entrypoints
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40387>
2026-05-07 15:49:20 +00:00
Lionel Landwerlin
f123030dcd anv: implement VK_KHR_device_address_commands
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40387>
2026-05-07 15:49:20 +00:00
Lionel Landwerlin
7adece7ce0 anv: fixup null address check
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40387>
2026-05-07 15:49:19 +00:00
Lionel Landwerlin
3ffca66b3c vulkan/runtime: fix invalid address flags value for CmdCopyBufferToImage2
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: a8e49be9d9 ("vulkan/runtime: add implementation of older entrypoints using KHR_DAC")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40387>
2026-05-07 15:49:19 +00:00
Icenowy Zheng
5d2cc50247 pvr: add dri options used by common WSI code
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The common Mesa Vulkan WSI code checks some DRI options.

Add them to the option list of the PVR driver.

Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
Reviewed-by: Simon Perretta <simon.perretta@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41197>
2026-05-07 15:33:01 +00:00
Icenowy Zheng
41ed38615b pvr: prohibit clang-format from touching the dri options list
The DRI options list is formatted specically and clang-format cannot
handle it properly.

Disable clang-format for this snippet.

Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
Reviewed-by: Simon Perretta <simon.perretta@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41197>
2026-05-07 15:33:01 +00:00
hmtheboy154
88f5e5986b pvr: add support for driconf for the Vulkan driver
Bringing force_vk_vendor as the first option, force_vk_devicename
will be added later

Signed-off-by: hmtheboy154 <buingoc67@gmail.com>
Reviewed-by: Simon Perretta <simon.perretta@imgtec.com>
[Icenowy: rebased on top of main]

Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41197>
2026-05-07 15:33:01 +00:00
Christoph Pillmayer
109af1b077 pan/kmod: Fix uninitialized timestamp info
The kernel looks at drm_panthor_timestamp_info::flags, so it can't be
uninitialized.

Fixes: 302127fe ("pan/kmod: Add timestamp uapi support")
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41418>
2026-05-07 13:37:25 +00:00
Faith Ekstrand
4714395eb8 pan/bi: Drop lower_index_to_offset from preprocess
Some checks are pending
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Reviewed-by: Ryan Mckeever <ryan.mckeever@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41320>
2026-05-07 13:11:08 +00:00
Faith Ekstrand
dd2d30656d panfrost: Handle pre-Valhall images and texel buffers in lower_res_indices
There's no point in having these as separate passes that live in the
compiler.  We already have lower_res_indices(), which is panfrost's
equivalent to panvk's descriptor lowering.  We can just do it there.

Reviewed-by: Ryan Mckeever <ryan.mckeever@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41320>
2026-05-07 13:11:08 +00:00
Faith Ekstrand
d0bdd18212 panfrost: Prefix valhall bits of lower_res_indices
Reviewed-by: Ryan Mckeever <ryan.mckeever@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41320>
2026-05-07 13:11:08 +00:00
Faith Ekstrand
4412f3bad7 panfrost: Take texture/sampler_index into account in lower_res_indices
We currently rely on nir_lower_tex_options::lower_index_to_offset but
there's really no reason for this.  Our pan_nir_res_handle() helper can
already take both an immediate and a dynamic index.

Reviewed-by: Ryan Mckeever <ryan.mckeever@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41320>
2026-05-07 13:11:08 +00:00
Faith Ekstrand
0a69efb22b panvk: Add MAX_VS_ATTRIBS to image indices in panvk_nir_lower_descriptors
It's only a couple lines of code since we're already doing this for
UBOs.  It doesn't need to be a separate pass.

Reviewed-by: Ryan Mckeever <ryan.mckeever@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41320>
2026-05-07 13:11:08 +00:00
Faith Ekstrand
c73d4e14f9 pan/nir/tex: Support full index+offset
Previously, we only supported one of the index or the offset source and
relied on lower_index_to_offset to ensure we only had one or the other.
However, now that we're doing things in NIR, it's trivial to support the
full index+offset form.

Reviewed-by: Ryan Mckeever <ryan.mckeever@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41320>
2026-05-07 13:11:08 +00:00
Pierre-Eric Pelloux-Prayer
61acf0e781 radeonsi: add tests subfolder and move AMD_TEST code inside
And move the exit(0) code to the si_tests function.

Reviewed-by: David Rosca <david.rosca@amd.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41133>
2026-05-07 14:18:21 +02:00
Pierre-Eric Pelloux-Prayer
61ae8f60d1 radeonsi/gfx: move static inline helpers to si_gfx.h
Reviewed-by: David Rosca <david.rosca@amd.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41133>
2026-05-07 14:18:19 +02:00
Pierre-Eric Pelloux-Prayer
b833aeb9de radeonsi/gfx: remove unnecessary u_stub usage
Everything inside the gfx folder isn't built when HAVE_GFX_COMPUTE
isn't present so we don't need to stub these methods.

Reviewed-by: David Rosca <david.rosca@amd.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41133>
2026-05-07 14:18:17 +02:00
Pierre-Eric Pelloux-Prayer
4c080ae32e radeonsi: move function prototypes from si_pipe.h to si_gfx.h
Reviewed-by: David Rosca <david.rosca@amd.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41133>
2026-05-07 14:18:15 +02:00
Pierre-Eric Pelloux-Prayer
714d3eb0b4 radeonsi: move more code to gfx subfolder
Anything related to shaders, compute, mesh, nir should be inside
this folder.

Reviewed-by: David Rosca <david.rosca@amd.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41133>
2026-05-07 14:18:09 +02:00
Pierre-Eric Pelloux-Prayer
79b09571bb radeonsi: move all multimedia files to mm
Reviewed-by: David Rosca <david.rosca@amd.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41133>
2026-05-07 14:18:08 +02:00
Pierre-Eric Pelloux-Prayer
e4def8a61c radeonsi: add si_context.c
And move out most si_context code to the new file.

Reviewed-by: David Rosca <david.rosca@amd.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41133>
2026-05-07 14:18:06 +02:00
Pierre-Eric Pelloux-Prayer
b2db3e1ddc radeonsi: add si_gfx_context.c and move code from si_pipe.c
Reviewed-by: David Rosca <david.rosca@amd.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41133>
2026-05-07 14:18:04 +02:00
Pierre-Eric Pelloux-Prayer
a335f4be7a radeonsi/gfx: move code from si_get to si_gfx_screen
These functions can be moved to the gfx subfolder and made static.

Reviewed-by: David Rosca <david.rosca@amd.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41133>
2026-05-07 14:18:02 +02:00
Pierre-Eric Pelloux-Prayer
d1c57f742e radeonsi/gfx: add si_gfx_screen.c
And move code specific to gfx/compute from radeonsi_screen_create_impl there.

ac_init_llvm_once has to stay in si_pipe.c because it has to be called very
early to avoid conflicts with u_queue initialisation.

Reviewed-by: David Rosca <david.rosca@amd.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41133>
2026-05-07 14:17:59 +02:00
Pierre-Eric Pelloux-Prayer
5f56a0e057 radeonsi: add si_resource_copy_buffer
Same as si_resource_copy_resource except it only supports buffers.

Also make sure that si_compute_clear_copy_buffer doesn't do
anything when has_gfx_compute is false.

Reviewed-by: David Rosca <david.rosca@amd.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41133>
2026-05-07 14:17:56 +02:00
Pierre-Eric Pelloux-Prayer
838ce62f3a radeonsi: extract si_init_gfx_caps from si_init_screen_caps
Reviewed-by: David Rosca <david.rosca@amd.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41133>
2026-05-07 14:17:54 +02:00
Pierre-Eric Pelloux-Prayer
a325be9548 radeonsi: move shader cache code to new file
Reviewed-by: David Rosca <david.rosca@amd.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41133>
2026-05-07 14:17:53 +02:00
Pierre-Eric Pelloux-Prayer
68a383531d radeonsi: add gfx subfolder
Same idea as for mm.

Reviewed-by: David Rosca <david.rosca@amd.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41133>
2026-05-07 14:17:47 +02:00
Pierre-Eric Pelloux-Prayer
4c08b87fe1 radeonsi: add si_init_screen_nir_options
Extract code from si_init_screen_get_functions to new helper.
The code assigning nir_options[] is moved out to help future
changes.

Reviewed-by: David Rosca <david.rosca@amd.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41133>
2026-05-07 14:17:45 +02:00
Pierre-Eric Pelloux-Prayer
e8cdd8ccb1 radeonsi: create a mm subfolder for multimedia code
Start moving code that's only for radeonsi multimedia support in this
folder to declutter si_pipe.c and si_get.c.

Reviewed-by: David Rosca <david.rosca@amd.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41133>
2026-05-07 14:17:42 +02:00
Pierre-Eric Pelloux-Prayer
b819ad62c2 radeonsi/vce: deal with has_gfx_compute being false
In this case the workaround can't be implemented so we must
report a failure.

Reviewed-by: David Rosca <david.rosca@amd.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41133>
2026-05-07 14:17:40 +02:00
Pierre-Eric Pelloux-Prayer
6e2d8c04be radeonsi: don't use staging texture when we can't blit
Reviewed-by: David Rosca <david.rosca@amd.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41133>
2026-05-07 14:17:38 +02:00
Pierre-Eric Pelloux-Prayer
3a1c466084 radeonsi: add has_gfx_compute property to si_screen
Reviewed-by: David Rosca <david.rosca@amd.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41133>
2026-05-07 14:17:36 +02:00
Pierre-Eric Pelloux-Prayer
931fc57f2a radeonsi: delay aux context initialization to first use
This avoids creating unneeded contexts.

Reviewed-by: David Rosca <david.rosca@amd.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41133>
2026-05-07 14:17:33 +02:00
Pierre-Eric Pelloux-Prayer
01c7a82760 gallium/vl: only release created sampler views
Reviewed-by: David Rosca <david.rosca@amd.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41133>
2026-05-07 14:17:31 +02:00