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radeonsi: move function prototypes from si_pipe.h to si_gfx.h

Browse source 
Reviewed-by: David Rosca <david.rosca@amd.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41133>
This commit is contained in:
Pierre-Eric Pelloux-Prayer 2026-04-15 13:18:06 +02:00
parent 714d3eb0b4
commit 4c080ae32e
19 changed files with 92 additions and 70 deletions
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2
src/gallium/drivers/radeonsi/gfx/si_blit.c
View file

@ -5,7 +5,7 @@
* SPDX-License-Identifier: MIT
*/
#include "gfx/si_gfx.h"
#include "si_gfx.h"
#include "si_pipe.h"
#include "util/format/u_format.h"
#include "util/u_log.h"

75
src/gallium/drivers/radeonsi/gfx/si_gfx.h
View file

@ -9,6 +9,7 @@
#include "util/mesa-blake3.h"
#include "util/u_stub_gfx_compute.h"
#include "ac_sqtt.h"
#ifdef __cplusplus
extern "C" {
@ -19,6 +20,46 @@ struct si_shader;
struct si_shader_selector;
struct si_context;
struct ac_llvm_compiler;
struct nir_shader;
struct radeon_cmdbuf;
struct si_sqtt_fake_pipeline;
struct pipe_resource;
struct pipe_blit_info;
struct si_texture;
struct pipe_box;
struct pipe_context;
enum si_blitter_op /* bitmask */
{
SI_SAVE_TEXTURES = 1,
SI_SAVE_FRAMEBUFFER = 2,
SI_SAVE_FRAGMENT_CONSTANT = 4,
SI_DISABLE_RENDER_COND = 8,
};
/* si_blit.c */
void si_blitter_begin(struct si_context *sctx, enum si_blitter_op op);
void si_blitter_end(struct si_context *sctx);
void si_init_blit_functions(struct si_context *sctx);
void gfx6_decompress_textures(struct si_context *sctx, unsigned shader_mask);
void gfx11_decompress_textures(struct si_context *sctx, unsigned shader_mask);
MESAPROC void si_decompress_subresource(struct pipe_context *ctx, struct pipe_resource *tex, unsigned planes,
unsigned level, unsigned first_layer, unsigned last_layer,
bool need_fmask_expand) TAILV;
MESAPROC void si_resource_copy_region(struct pipe_context *ctx, struct pipe_resource *dst,
unsigned dst_level, unsigned dstx, unsigned dsty, unsigned dstz,
struct pipe_resource *src, unsigned src_level,
const struct pipe_box *src_box) TAILV;
MESAPROC void si_gfx_copy_image(struct si_context *sctx, struct pipe_resource *dst,
unsigned dst_level, unsigned dstx, unsigned dsty, unsigned dstz,
struct pipe_resource *src, unsigned src_level,
const struct pipe_box *src_box) TAILV;
MESAPROC void si_decompress_dcc(struct si_context *sctx, struct si_texture *tex) TAILV;
void si_flush_implicit_resources(struct si_context *sctx);
MESAPROC void si_gfx_blit(struct pipe_context *ctx, const struct pipe_blit_info *info) TAILV;
/* si_nir_optim.c */
bool si_nir_is_output_const_if_tex_is_const(struct nir_shader *shader, float *in, float *out, int *texunit);
/* si_gfx_context.c */
MESAPROC bool si_init_gfx_context(struct si_screen *sscreen, struct si_context *sctx, unsigned flags) TAILB;
@ -46,6 +87,40 @@ bool si_shader_cache_load_shader(struct si_screen *sscreen, unsigned char ir_bla
void si_shader_cache_insert_shader(struct si_screen *sscreen, unsigned char ir_blake3_cache_key[BLAKE3_KEY_LEN],
struct si_shader *shader, bool insert_into_disk_cache);
/* si_sqtt.c */
void si_sqtt_write_event_marker(struct si_context* sctx, struct radeon_cmdbuf *rcs,
enum rgp_sqtt_marker_event_type api_type,
uint32_t vertex_offset_user_data,
uint32_t instance_offset_user_data,
uint32_t draw_index_user_data);
bool si_sqtt_register_pipeline(struct si_context* sctx, struct si_sqtt_fake_pipeline *pipeline,
uint32_t *gfx_sh_offsets);
bool si_sqtt_pipeline_is_registered(struct ac_sqtt *sqtt,
uint64_t pipeline_hash);
void si_sqtt_describe_pipeline_bind(struct si_context* sctx, uint64_t pipeline_hash, int bind_point);
void
si_write_event_with_dims_marker(struct si_context* sctx, struct radeon_cmdbuf *rcs,
enum rgp_sqtt_marker_event_type api_type,
uint32_t x, uint32_t y, uint32_t z);
void
si_write_user_event(struct si_context* sctx, struct radeon_cmdbuf *rcs,
enum rgp_sqtt_marker_user_event_type type,
const char *str, int len);
MESAPROC void
si_sqtt_describe_barrier_start(struct si_context* sctx, struct radeon_cmdbuf *rcs) TAILV;
MESAPROC void
si_sqtt_describe_barrier_end(struct si_context* sctx, struct radeon_cmdbuf *rcs, unsigned flags) TAILV;
bool si_init_sqtt(struct si_context *sctx);
void si_destroy_sqtt(struct si_context *sctx);
MESAPROC void si_handle_sqtt(struct si_context *sctx, struct radeon_cmdbuf *rcs) TAILV;
/* si_mesh_shader.c */
void si_init_task_mesh_shader_functions(struct si_context *sctx);
/* si_nir_mediump.c */
void si_nir_lower_mediump_io_default(struct nir_shader *nir);
void si_nir_lower_mediump_io_option(struct nir_shader *nir);
#ifdef __cplusplus
}
#endif

1
src/gallium/drivers/radeonsi/gfx/si_mesh_shader.c
View file

@ -7,6 +7,7 @@
#include "si_pipe.h"
#include "si_build_pm4.h"
#include "si_query.h"
#include "si_gfx.h"
#include "util/u_upload_mgr.h"
#define SI_MESH_PIPELINE_STATE_DIRTY_MASK \

2
src/gallium/drivers/radeonsi/gfx/si_nir_mediump.c
View file

@ -3,7 +3,7 @@
*
* SPDX-License-Identifier: MIT
*/
#include "si_pipe.h"
#include "si_gfx.h"
#include "nir.h"
#include "nir/nir_xfb_info.h"

2
src/gallium/drivers/radeonsi/gfx/si_nir_optim.c
View file

@ -4,7 +4,7 @@
* SPDX-License-Identifier: MIT
*/
#include "si_pipe.h"
#include "si_gfx.h"
#include "nir.h"
#include "nir_builder.h"
#include "nir_worklist.h"

1
src/gallium/drivers/radeonsi/gfx/si_sqtt.c
View file

@ -4,6 +4,7 @@
* SPDX-License-Identifier: MIT
*/
#include "si_gfx.h"
#include "ac_cmdbuf_cp.h"
#include "ac_shader_util.h"
#include "amd_family.h"

2
src/gallium/drivers/radeonsi/mm/radeon_vce.c
View file

@ -10,7 +10,7 @@
#include "pipe/p_video_codec.h"
#include "radeon_bitstream.h"
#include "si_pipe.h"
#include "gfx/si_gfx.h"
#include "util/u_memory.h"
#include "vl/vl_video_buffer.h"
#include "si_video.h"

1
src/gallium/drivers/radeonsi/si_barrier.c
View file

@ -6,6 +6,7 @@
#include "si_build_pm4.h"
#include "si_query.h"
#include "gfx/si_gfx.h"
static struct si_resource *si_get_wait_mem_scratch_bo(struct si_context *ctx,
struct radeon_cmdbuf *cs, bool is_secure)

1
src/gallium/drivers/radeonsi/si_clear.c
View file

@ -4,6 +4,7 @@
* SPDX-License-Identifier: MIT
*/
#include "gfx/si_gfx.h"
#include "si_pipe.h"
#include "util/format/u_format.h"
#include "util/u_pack_color.h"

1
src/gallium/drivers/radeonsi/si_cp_utils.c
View file

@ -5,6 +5,7 @@
*/
#include "si_pipe.h"
#include "gfx/si_gfx.h"
#include "ac_cmdbuf_cp.h"
void si_cp_release_mem_pws(struct si_context *sctx, struct radeon_cmdbuf *cs,

1
src/gallium/drivers/radeonsi/si_descriptors.c
View file

@ -36,6 +36,7 @@
*/
#include "si_pipe.h"
#include "gfx/si_gfx.h"
#include "si_build_pm4.h"
#include "sid.h"
#include "util/format/u_format.h"

1
src/gallium/drivers/radeonsi/si_fence.c
View file

@ -5,6 +5,7 @@
*/
#include "si_pipe.h"
#include "gfx/si_gfx.h"
#include "ac_cmdbuf_cp.h"
#include "util/os_time.h"
#include "util/u_memory.h"

1
src/gallium/drivers/radeonsi/si_gfx_cs.c
View file

@ -5,6 +5,7 @@
* SPDX-License-Identifier: MIT
*/
#include "gfx/si_gfx.h"
#include "si_build_pm4.h"
#include "si_pipe.h"
#include "sid.h"

66
src/gallium/drivers/radeonsi/si_pipe.h
View file

@ -1379,38 +1379,6 @@ void si_barrier_before_image_fast_clear(struct si_context *sctx, unsigned types)
void si_barrier_after_image_fast_clear(struct si_context *sctx);
void si_init_barrier_functions(struct si_context *sctx);
/* si_blit.c */
enum si_blitter_op /* bitmask */
{
SI_SAVE_TEXTURES = 1,
SI_SAVE_FRAMEBUFFER = 2,
SI_SAVE_FRAGMENT_CONSTANT = 4,
SI_DISABLE_RENDER_COND = 8,
};
void si_blitter_begin(struct si_context *sctx, enum si_blitter_op op);
void si_blitter_end(struct si_context *sctx);
void si_init_blit_functions(struct si_context *sctx);
void gfx6_decompress_textures(struct si_context *sctx, unsigned shader_mask);
void gfx11_decompress_textures(struct si_context *sctx, unsigned shader_mask);
MESAPROC void si_decompress_subresource(struct pipe_context *ctx, struct pipe_resource *tex, unsigned planes,
unsigned level, unsigned first_layer, unsigned last_layer,
bool need_fmask_expand) TAILV;
MESAPROC void si_resource_copy_region(struct pipe_context *ctx, struct pipe_resource *dst,
unsigned dst_level, unsigned dstx, unsigned dsty, unsigned dstz,
struct pipe_resource *src, unsigned src_level,
const struct pipe_box *src_box) TAILV;
void si_gfx_copy_image(struct si_context *sctx, struct pipe_resource *dst,
unsigned dst_level, unsigned dstx, unsigned dsty, unsigned dstz,
struct pipe_resource *src, unsigned src_level,
const struct pipe_box *src_box);
MESAPROC void si_decompress_dcc(struct si_context *sctx, struct si_texture *tex) TAILV;
void si_flush_implicit_resources(struct si_context *sctx);
MESAPROC void si_gfx_blit(struct pipe_context *ctx, const struct pipe_blit_info *info) TAILV;
/* si_nir_optim.c */
bool si_nir_is_output_const_if_tex_is_const(struct nir_shader *shader, float *in, float *out, int *texunit);
/* si_buffer.c */
bool si_cs_is_buffer_referenced(struct si_context *sctx, struct pb_buffer_lean *buf,
unsigned usage);
@ -1697,40 +1665,6 @@ bool si_texture_disable_dcc(struct si_context *sctx, struct si_texture *tex);
void si_init_screen_texture_functions(struct si_screen *sscreen);
void si_init_context_texture_functions(struct si_context *sctx);
/* si_sqtt.c */
void si_sqtt_write_event_marker(struct si_context* sctx, struct radeon_cmdbuf *rcs,
enum rgp_sqtt_marker_event_type api_type,
uint32_t vertex_offset_user_data,
uint32_t instance_offset_user_data,
uint32_t draw_index_user_data);
bool si_sqtt_register_pipeline(struct si_context* sctx, struct si_sqtt_fake_pipeline *pipeline,
uint32_t *gfx_sh_offsets);
bool si_sqtt_pipeline_is_registered(struct ac_sqtt *sqtt,
uint64_t pipeline_hash);
void si_sqtt_describe_pipeline_bind(struct si_context* sctx, uint64_t pipeline_hash, int bind_point);
void
si_write_event_with_dims_marker(struct si_context* sctx, struct radeon_cmdbuf *rcs,
enum rgp_sqtt_marker_event_type api_type,
uint32_t x, uint32_t y, uint32_t z);
MESAPROC void
si_write_user_event(struct si_context* sctx, struct radeon_cmdbuf *rcs,
enum rgp_sqtt_marker_user_event_type type,
const char *str, int len) TAILV;
MESAPROC void
si_sqtt_describe_barrier_start(struct si_context* sctx, struct radeon_cmdbuf *rcs) TAILV;
MESAPROC void
si_sqtt_describe_barrier_end(struct si_context* sctx, struct radeon_cmdbuf *rcs, unsigned flags) TAILV;
MESAPROC bool si_init_sqtt(struct si_context *sctx) TAILB;
MESAPROC void si_destroy_sqtt(struct si_context *sctx) TAILV;
MESAPROC void si_handle_sqtt(struct si_context *sctx, struct radeon_cmdbuf *rcs) TAILV;
/* si_mesh_shader.c */
MESAPROC void si_init_task_mesh_shader_functions(struct si_context *sctx) TAILV;
/* si_nir_mediump.c */
MESAPROC void si_nir_lower_mediump_io_default(nir_shader *nir) TAILV;
MESAPROC void si_nir_lower_mediump_io_option(nir_shader *nir) TAILV;
/*
* common helpers
*/

1
src/gallium/drivers/radeonsi/si_sdma_copy_image.c
View file

@ -6,6 +6,7 @@
*/
#include "si_pipe.h"
#include "gfx/si_gfx.h"
#include "util/u_memory.h"
#include "ac_cmdbuf_sdma.h"

1
src/gallium/drivers/radeonsi/si_state.c
View file

@ -6,6 +6,7 @@
#include "si_build_pm4.h"
#include "si_query.h"
#include "gfx/si_gfx.h"
#include "gfx/si_shader_internal.h"
#include "sid.h"
#include "util/fast_idiv_by_const.h"

1
src/gallium/drivers/radeonsi/si_state_draw.cpp
View file

@ -16,6 +16,7 @@
#include "ac_rtld.h"
#include "si_build_pm4.h"
#include "si_tracepoints.h"
#include "gfx/si_gfx.h"
#if (GFX_VER == 6)
#define GFX(name) name##GFX6

1
src/gallium/drivers/radeonsi/si_test_image_copy_region.c
View file

@ -7,6 +7,7 @@
/* This file implements randomized texture blit tests. */
#include "si_pipe.h"
#include "gfx/si_gfx.h"
#include "util/rand_xor.h"
#include "util/u_surface.h"
#include "amd/addrlib/inc/addrtypes.h"

1
src/gallium/drivers/radeonsi/si_texture.c
View file

@ -6,6 +6,7 @@
*/
#include "drm-uapi/drm_fourcc.h"
#include "gfx/si_gfx.h"
#include "si_pipe.h"
#include "si_query.h"
#include "frontend/drm_driver.h"