Rework the constant register encoding to track per-channel ownership
(I915_CONSTFLAG_IMM / I915_CONSTFLAG_USER_CH) instead of whole-register
flags, allowing compiler immediates and user UBO values to share a
constant register on different channels. Update emit_constants() to
handle per-channel source selection at upload time.
Add i915_emit_const1f_prefer() for packing scalar constants into a
preferred register, reducing dual-constant conflicts.
Move i915_program_error(), i915_use_passthrough_shader(), and negate()
from i915_fpc_translate.c to shared locations (i915_fpc_emit.c /
i915_fpc.h) so the NIR backend can use them.
Fix i915_emit_texld() to use a utemp instead of a temp register for
texcoord swizzle copies, avoiding unnecessary tex indirect phase
boundaries. Add a fallback path that copies to a utemp when bumping
the phase count would exceed the hardware limit.
Add nr_alu_insn, nr_tex_insn, nr_tex_indirect, nr_temps, writes_z,
and input semantic tracking to i915_fragment_shader for use by the
NIR backend's multi-variant comparison framework.
Assisted-by: Claude
i915_fpc_optimize_mov_before_tex replaces a MOV+TEX pair with a
direct TEX from the input register when the MOV copies from the
input with identity swizzle. But it only checked the source swizzle,
not the MOV's writemask. When the MOV wrote a subset of the channels
the TEX reads (e.g., MOV TEMP.y, IN.y before a 2D TEX that reads
XY), the optimization replaced the TEX source with IN, losing the X
channel that was set by a different MOV.
This caused incorrect texture sampling coordinates in shaders with
multi-MOV texcoord construction (blur filters, shadow maps, etc.).
Fix: verify the MOV's dest writemask covers all channels the TEX
instruction reads before applying the optimization.
Assisted-by: Claude
The TGSI compiler rejected empty fragment shaders (num_instructions
== 1, just TGSI_END) as errors. Instead, emit a passthrough program.
Assisted-by: Claude
Report actual instruction counts (alu+tex) instead of program dwords/3,
add a separate "alu" field for the 64-instruction bottleneck metric, and
fix "temps" to use the actual temp register count instead of
util_last_bit (highest register number).
Before: "69 inst, 2 tex, 3 tex_indirect, 4 temps, 5 const"
After: "21 instructions, 19 alu, 2 tex, 2 tex_indirect, 16 temps, 3 const"
Assisted-by: Claude
draw_vs.c already handles the non-native-integer NIR→TGSI conversion
internally, so i915 doesn't need to do it. keep nir_lower_point_size
(i915-specific lowering) and pass the result to draw as NIR.
Assisted-by: Claude
This removes 18042479026 as we don't utilize BRW_AOP_MOV in compiler
and adds missing xe2 entries for 14025112257.
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41281>
The common Mesa Vulkan WSI code checks some DRI options.
Add them to the option list of the PVR driver.
Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
Reviewed-by: Simon Perretta <simon.perretta@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41197>
The DRI options list is formatted specically and clang-format cannot
handle it properly.
Disable clang-format for this snippet.
Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
Reviewed-by: Simon Perretta <simon.perretta@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41197>
Bringing force_vk_vendor as the first option, force_vk_devicename
will be added later
Signed-off-by: hmtheboy154 <buingoc67@gmail.com>
Reviewed-by: Simon Perretta <simon.perretta@imgtec.com>
[Icenowy: rebased on top of main]
Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41197>
The kernel looks at drm_panthor_timestamp_info::flags, so it can't be
uninitialized.
Fixes: 302127fe ("pan/kmod: Add timestamp uapi support")
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41418>
There's no point in having these as separate passes that live in the
compiler. We already have lower_res_indices(), which is panfrost's
equivalent to panvk's descriptor lowering. We can just do it there.
Reviewed-by: Ryan Mckeever <ryan.mckeever@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41320>
We currently rely on nir_lower_tex_options::lower_index_to_offset but
there's really no reason for this. Our pan_nir_res_handle() helper can
already take both an immediate and a dynamic index.
Reviewed-by: Ryan Mckeever <ryan.mckeever@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41320>
It's only a couple lines of code since we're already doing this for
UBOs. It doesn't need to be a separate pass.
Reviewed-by: Ryan Mckeever <ryan.mckeever@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41320>
Previously, we only supported one of the index or the offset source and
relied on lower_index_to_offset to ensure we only had one or the other.
However, now that we're doing things in NIR, it's trivial to support the
full index+offset form.
Reviewed-by: Ryan Mckeever <ryan.mckeever@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41320>
Everything inside the gfx folder isn't built when HAVE_GFX_COMPUTE
isn't present so we don't need to stub these methods.
Reviewed-by: David Rosca <david.rosca@amd.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41133>
And move code specific to gfx/compute from radeonsi_screen_create_impl there.
ac_init_llvm_once has to stay in si_pipe.c because it has to be called very
early to avoid conflicts with u_queue initialisation.
Reviewed-by: David Rosca <david.rosca@amd.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41133>
Same as si_resource_copy_resource except it only supports buffers.
Also make sure that si_compute_clear_copy_buffer doesn't do
anything when has_gfx_compute is false.
Reviewed-by: David Rosca <david.rosca@amd.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41133>
Extract code from si_init_screen_get_functions to new helper.
The code assigning nir_options[] is moved out to help future
changes.
Reviewed-by: David Rosca <david.rosca@amd.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41133>
Start moving code that's only for radeonsi multimedia support in this
folder to declutter si_pipe.c and si_get.c.
Reviewed-by: David Rosca <david.rosca@amd.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41133>
The next commits will make it possible that sctx->gfx_cs isn't
initialized so we can't assume anymore that amdgpu_cs() always
return a valid cs.
Reviewed-by: David Rosca <david.rosca@amd.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41133>
Per Vulkan spec, the pipeline sample mask applies to all rasterization
sample counts, including single-sample. Drop the msaa-conditional clamp
that forced the sample mask to UINT16_MAX when rasterizationSamples == 1
and just use vk_dynamic_graphics_state's value directly. The default
when no static pSampleMask is provided is already all-ones, so existing
behaviour is preserved for pipelines that don't set the mask.
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40882>
It's possible to use a shader that has ViewIndex input when multiview
isn't enabled. According to the Vulkan specification, when multiview
isn't enabled in a renderpass, the value of the ViewIndex input should
be 0.
However currently the driver does not emit execution of the PDS code
setting up view index, which leads to stale value to remain in
ViewIndex.
Setup the PDS code for setting view index and emit the command stream
for executing that PDS code when the shader wants ViewIndex, even if
multiview isn't enabled.
Fixes: 9d48088428 ("pvr: add view index support for vertex shaders")
Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
Reviewed-by: Nick Hamilton <nick.hamilton@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40972>
