For now linking is just removing unused varyings between stages.
shader-db results BDW:
total instructions in shared programs: 13198288 -> 13191693 (-0.05%)
instructions in affected programs: 48325 -> 41730 (-13.65%)
helped: 473
HURT: 0
total cycles in shared programs: 541184926 -> 541159260 (-0.00%)
cycles in affected programs: 213238 -> 187572 (-12.04%)
helped: 435
HURT: 8
V2:
- lower indirects on demoted inputs as well as outputs.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This will allow us to insert a nir linking step in brw_link_shader().
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
This will help us call gather info at a later point and allow us
to do some linking in nir.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
The initial helpers add support for removing unused varyings between
stages.
V2:
- Moved the io mask helper function into this file rather than
nir.h so it's not used elsewhere considering it doesn't handle
all corner cases.
- Use bitmask rather than hash table to handle tcs outputs (Ken)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This will be used by the nir linking pass so that we don't remove
otherwise unused varyings.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
Will be used in nir link pass to decided if we can remove a varying
or not.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
This marks the end of code sharing between r600 and radeonsi.
It's getting difficult to work on radeonsi without breaking r600.
A lot of functions had to be renamed to prevent linker conflicts.
There are also minor cleanups.
Acked-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
do_flush_locked isn't a great name - especially given that there's no
locking going on in our code relating to execbuf.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
We have a nice utility function for this, which eliminates the need for
locking stuff. This isn't really performance critical, but it's less
code to use the atomic.
p_atomic_inc_return does pre-increment rather than post-increment, so we
change screen->program_id to be initialized to 0 instead of 1. At which
point, we can just delete the initialization because intel_screen is
rzalloc'd.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
There's no real advantage or disadvantage here, it's just for stylistic
consistency with the rest of the codebase.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Supported in JitGatherVertices(); FetchJit::JitLoadVertices() may require
similar changes, will need address this if it is determined that this
path is still in use.
Handle Force Sequential Access in FetchJit::Create.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Move structure, as the size is significantly reduced due to dynamic
allocation of the GS buffers.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
One piglit regression, which was a false pass:
spec@glsl-1.50@execution@geometry@dynamic_input_array_index
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
This is needed since we don't update the number of viewports/scissors
when they are set dynamically (according to the spec). In the following
scenario:
* vkCmdSetViewport()
* vkCmdClearColorImage() (or any other meta operations)
The viewports/scissors weren't saved correctly because no pipeline
was bound before, and thus the number of viewports/scissors were 0.
This fixes a regression with:
dEQP-VK.draw.negative_viewport_height.front_ccw_cull_back
Fixes: 60878dd00c ("radv: do not update the number of viewports in vkCmdSetViewport()")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
String handling has changed on python3.
Before this patch, on python3:
#define MESA_GIT_SHA1 "git-b'b99dcbfeb3'"
After:
#define MESA_GIT_SHA1 "git-b99dcbfeb3"
(No change on python2, it always looked ok)
Cc: Jose Fonseca <jfonseca@vmware.com>
Fixes: b99dcbfeb3 "build: Convert git_sha1_gen script to Python."
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Scaling between interlaced buffers, esp. for scale-up, because
blit will scale up top filed and bottom field separately. it'll
result in the weaving for these buffer with lack of accuracy.
So use shader deint for the case.
Acked-by: Christian König <christian.koenig@amd.com>
Before it's impossible to transcode an interlaced video, becasue if
in order for encoder to work, we have to force buffer to progessive,
but the deint with buffer from I to P is missing. Now along With
the new YUV deint full function, it works with weave and bob deint.
Also this will benefit transcoding video with scaling parameters.
Acked-by: Christian König <christian.koenig@amd.com>
We also set src rectangle explicitly just in case of the mismatch
of size between interlaced buffer and progressive buffer
Acked-by: Christian König <christian.koenig@amd.com>
Spec adding corner cases ...
Fixes: 969537d935 "radv: Add support for more DCC compression with VK_KHR_image_format_list."
Reviewed-by: Dave Airlie <airlied@redhat.com>
I tested this 10 times with
./deqp-vk --deqp-case=dEQP-VK.texture.filtering.3d.formats.r4g4b4a4*
and one full run of CTS, seems the issue is gone.
Also reduces CTS runtime by 30% or so.
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
These changes were generated using python's `2to3` tool.
Suggested-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
These changes were generated using python's `2to3` tool.
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
These changes were generated using python's `2to3` tool.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102852
Reported-by: Alex Granni <liviuprodea@yahoo.com>
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Otherwise, the disasm string is NULL for meta shaders.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
