Commit graph

16408 commits

Author SHA1 Message Date
Vinson Lee
2faa2b4f7e gallium/util: Use GCC built-in functions for NaN and infinity.
This patch fixes this build failure with Intel Compiler.

src/gallium/auxiliary/util/u_format_tests.c(903): error: floating-point operation result is out of range
     {PIPE_FORMAT_R16_FLOAT, PACKED_1x16(0xffff), PACKED_1x16(0x7c01), UNPACKED_1x1(        NAN, 0.0, 0.0, 1.0)},

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: José Fonseca <jfonseca@vmware.com>
2012-07-30 23:27:19 -07:00
Tom Stellard
cd0949eb28 radeon/llvm: Cleanup AMDIL.h 2012-07-30 21:10:14 +00:00
Tom Stellard
2f921101c0 radeon/llvm: Rename all AMDIL* classes to AMDGPU* 2012-07-30 21:10:14 +00:00
Tom Stellard
b72ab79d73 radeon/llvm: Merge AMDILSubtarget into AMDGPUSubtarget 2012-07-30 21:10:13 +00:00
Tom Stellard
27ae41c83d radeon/llvm: Merge AMDILTargetLowering class into AMDGPUTargetLowering 2012-07-30 21:10:13 +00:00
Tom Stellard
c96490e3b5 radeon/llvm: Remove IL_cmp DAG node 2012-07-30 21:10:13 +00:00
Tom Stellard
aece7970eb radeon/llvm: Cleanup and reorganize AMDIL .td files 2012-07-30 21:10:13 +00:00
Tom Stellard
0ce6e50601 radeon/llvm: Remove lowering code for unsupported features
e.g. function calls, load/store from stack
2012-07-30 21:10:08 +00:00
Tom Stellard
caeaf43dad radeon/llvm: Remove AMDILVersion.td 2012-07-30 20:31:57 +00:00
Tom Stellard
c3111eb639 radeon/llvm: Remove AMDILAlgorithms.tpp 2012-07-30 20:31:57 +00:00
Tom Stellard
ac669c32c6 radeon/llvm: Merge AMDILInstrInfo.cpp into AMDGPUInstrInfo.cpp 2012-07-30 20:31:57 +00:00
Tom Stellard
3a0187b1b5 radeon/llvm: Merge AMDILRegisterInfo into AMDGPURegisterInfo 2012-07-30 20:31:57 +00:00
Tom Stellard
9c42fb6f26 radeon/llvm: Change the tablegen target from AMDIL to AMDGPU 2012-07-30 20:31:56 +00:00
Christian König
86490bc150 radeonsi: fix db and stencil setup v2
v2: fix tiling for small pitches, that finally makes
    glxgears and readPixSanity work

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2012-07-30 15:02:04 +02:00
Christian König
7dace3a3cf radeonsi: fix stencil op mapping
Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2012-07-30 15:02:00 +02:00
Christian König
ad15c8c0f1 radeonsi: fix assertion in si_bind_vs_sampler
Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2012-07-30 15:01:55 +02:00
Christian König
1fb8ee62fa radeonsi: fix shader binding
Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2012-07-30 15:01:51 +02:00
Christian König
f18fd255cf radeonsi: fix dummy export in shaders v2
v2: add assertion for vertex shader

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2012-07-30 15:01:34 +02:00
Christian König
b15e3ae5b4 radeonsi: fix vertex buffer and elements
Let's just use the T# descriptors until we get a fetch shader.

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2012-07-30 14:45:32 +02:00
Christian König
d51b9b70d5 radeonsi: fix shader size and handling
We should always upload the shader here.

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2012-07-30 14:45:08 +02:00
Christian König
fe41287ffa radeonsi: rename r600_resource to si_resource
Also split it into seperate header and add
some helper functions.

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2012-07-30 14:44:38 +02:00
Christoph Bumiller
5d5af7d359 gallium: specify resource_resolve destination via a pipe_surface
The format member of pipe_surface may differ from that of the
pipe_resource, which is used to communicate, for instance, whether
sRGB encode should be enabled in the resolve operation or not.

Fixes resolve to sRGB surfaces in mesa/st when GL_FRAMEBUFFER_SRGB
is disabled.

Reviewed-by: Brian Paul <brianp@vmware.com>
2012-07-28 14:58:18 +02:00
Christoph Bumiller
acd66ec033 nv50: fix depth/stencil multisample memory storage types
Leftover from libdrm_nouveau v2 interface change.
2012-07-28 13:14:03 +02:00
Christoph Bumiller
cd3d85b63d nv50: fix resource_resolve shader start offsets 2012-07-28 13:11:56 +02:00
Tom Stellard
fdd8df20e4 r600g: Emit dispatch state for compute directly to the cs
We no longer rely on an evergreen_compute_resource for emitting dispatch
state.

Reviewed-by: Marek Olšák <maraeo@gmail.com>
2012-07-27 17:08:09 +00:00
Tom Stellard
dc0b8a4628 r600g: Initialize VGT_PRIMITIVE_TYPE in the start_cs_cmd atom
The value of this register will always be DI_PT_POINTLIST for compute
shaders.

Reviewed-by: Marek Olšák <maraeo@gmail.com>
2012-07-27 17:08:09 +00:00
Tom Stellard
d3b0130491 r600g: Atomize compute shader state
Reviewed-by: Marek Olšák <maraeo@gmail.com>
2012-07-27 17:08:09 +00:00
Tom Stellard
5497391067 r600g: Add helper functions for emitting compute SET_CONTEXT packets
Reviewed-by: Marek Olšák <maraeo@gmail.com>
2012-07-27 17:08:09 +00:00
Tom Stellard
c9ef27276f radeon/llvm: Add instruction defs for branches on SI 2012-07-27 17:08:09 +00:00
Tom Stellard
ee0f0f03c6 radeon/llvm: Fix VOPC and V_CNDMASK encoding 2012-07-27 17:08:09 +00:00
Tom Stellard
d4bdd09d47 radeon/llvm: Assert if we try to copy SCC reg 2012-07-27 17:08:09 +00:00
Tom Stellard
fd1f19a191 radeon/llvm: Add SI DAG optimizations for setcc, select_cc
These are needed for correctly lowering branch instructions in some
cases.
2012-07-27 17:08:08 +00:00
Tom Stellard
cd5d4c5073 radeon/llvm: Add support for encoding SI branch instructions 2012-07-27 17:08:08 +00:00
Tom Stellard
50ff2dc0a4 radeon/llvm: Add special nodes for SALU operations on VCC
The VCC register is tricky because the SALU views it as 64-bit, but the
VALU views it as 1-bit.  In order to deal with this we've added some
special bitcast and binary operations to help convert from the 64-bit
SALU view to the 1-bit VALU view and vice versa.
2012-07-27 17:08:08 +00:00
Tom Stellard
c424975572 radeon/llvm: Add i1 registers for SI. 2012-07-27 17:08:08 +00:00
Tom Stellard
bdda1cb914 radeon/llvm: Fix CCReg definitions on SI 2012-07-27 17:08:08 +00:00
Tom Stellard
ae9be358f2 radeonsi: Enable PIPE_SHADER_CAP_INTEGERS 2012-07-27 17:08:08 +00:00
Tom Stellard
022b54359a radeonsi: Add support for loading integers from constant memory 2012-07-27 17:08:07 +00:00
Tom Stellard
ad95bcb31f radeon/llvm: Add bitconvert patterns for SI 2012-07-27 17:08:07 +00:00
Tom Stellard
4cab682184 radeon/llvm: Add custom lowering for SELECT_CC nodes on SI 2012-07-27 17:08:07 +00:00
Tom Stellard
ba76684292 radeon/llvm: Move conditional pattern leafs to common tablegen file 2012-07-27 17:08:07 +00:00
Tom Stellard
d36455ba2c radeon/llvm: Implement getSetCCResultType for SI 2012-07-27 17:08:07 +00:00
Tom Stellard
e8825ce6e1 radeon/llvm: Custom lower BR_CC for SI 2012-07-27 17:08:07 +00:00
Tom Stellard
87272e9e25 radeon/llvm: Move lowering of BR_CC node to R600ISelLowering
SI will handle BR_CC different from R600, so we need to move it
out of the shared instruction selector.
2012-07-27 17:08:07 +00:00
Tom Stellard
92823fb72a radeon/llvm: Move lowering of SETCC node to R600ISelLowering
SI will handle SETCC different from R600, so we need to move it
out of the shared instruction selector.
2012-07-27 17:08:06 +00:00
Tom Stellard
46d12c99a2 radeon/llvm: Use correct node type when lowering SETCC 2012-07-27 17:08:06 +00:00
Tom Stellard
47d1b0a809 radeon/llvm: Move LowerSELECT_CC into R600ISelLowering
SI will handle SELECT_CC different from R600, so we need to move it out
of the shared instruction selector.
2012-07-27 17:08:06 +00:00
Eric Anholt
11ff18fcf5 automake: Remove OPT_FLAGS.
If you want to change your compiler arguments, just set CFLAGS/CXXFLAGS.
Having Mesa have this separate variable is a great way to have your arguments
not thoroughly propagated to all compiler invocations.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-07-26 17:30:06 -07:00
Eric Anholt
87a1c4f233 automake: Remove ARCH_FLAGS.
In all current uses, it was appended to CFLAGS, which already had -m32.  If
you want to do some other flag supplied to compiler invocations, there's
CFLAGS/CXXFLAGS.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-07-26 17:30:06 -07:00
Brian Paul
f37f1a7209 svga: initialize svga_compile_key to zeros to be safe 2012-07-26 16:00:31 -06:00