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radeon/llvm: Move conditional pattern leafs to common tablegen file
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d36455ba2c
commit
ba76684292
2 changed files with 41 additions and 41 deletions
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@ -33,6 +33,47 @@ class AMDGPUShaderInst <dag outs, dag ins, string asm, list<dag> pattern>
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}
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def COND_EQ : PatLeaf <
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(cond),
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[{switch(N->get()){{default: return false;
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case ISD::SETOEQ: case ISD::SETUEQ:
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case ISD::SETEQ: return true;}}}]
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>;
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def COND_NE : PatLeaf <
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(cond),
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[{switch(N->get()){{default: return false;
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case ISD::SETONE: case ISD::SETUNE:
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case ISD::SETNE: return true;}}}]
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>;
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def COND_GT : PatLeaf <
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(cond),
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[{switch(N->get()){{default: return false;
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case ISD::SETOGT: case ISD::SETUGT:
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case ISD::SETGT: return true;}}}]
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>;
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def COND_GE : PatLeaf <
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(cond),
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[{switch(N->get()){{default: return false;
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case ISD::SETOGE: case ISD::SETUGE:
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case ISD::SETGE: return true;}}}]
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>;
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def COND_LT : PatLeaf <
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(cond),
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[{switch(N->get()){{default: return false;
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case ISD::SETOLT: case ISD::SETULT:
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case ISD::SETLT: return true;}}}]
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>;
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def COND_LE : PatLeaf <
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(cond),
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[{switch(N->get()){{default: return false;
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case ISD::SETOLE: case ISD::SETULE:
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case ISD::SETLE: return true;}}}]
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>;
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class Constants {
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int TWO_PI = 0x40c90fdb;
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int PI = 0x40490fdb;
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@ -130,47 +130,6 @@ def TEX_SHADOW : PatLeaf<
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}]
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>;
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def COND_EQ : PatLeaf <
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(cond),
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[{switch(N->get()){{default: return false;
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case ISD::SETOEQ: case ISD::SETUEQ:
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case ISD::SETEQ: return true;}}}]
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>;
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def COND_NE : PatLeaf <
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(cond),
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[{switch(N->get()){{default: return false;
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case ISD::SETONE: case ISD::SETUNE:
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case ISD::SETNE: return true;}}}]
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>;
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def COND_GT : PatLeaf <
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(cond),
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[{switch(N->get()){{default: return false;
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case ISD::SETOGT: case ISD::SETUGT:
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case ISD::SETGT: return true;}}}]
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>;
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def COND_GE : PatLeaf <
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(cond),
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[{switch(N->get()){{default: return false;
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case ISD::SETOGE: case ISD::SETUGE:
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case ISD::SETGE: return true;}}}]
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>;
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def COND_LT : PatLeaf <
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(cond),
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[{switch(N->get()){{default: return false;
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case ISD::SETOLT: case ISD::SETULT:
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case ISD::SETLT: return true;}}}]
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>;
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def COND_LE : PatLeaf <
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(cond),
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[{switch(N->get()){{default: return false;
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case ISD::SETOLE: case ISD::SETULE:
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case ISD::SETLE: return true;}}}]
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>;
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class EG_CF_RAT <bits <8> cf_inst, bits <6> rat_inst, bits<4> rat_id, dag outs,
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dag ins, string asm, list<dag> pattern> :
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InstR600ISA <outs, ins, asm, pattern>
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