This enables MCS support on XeHP, now that MCS can be created with a
tiling supported by that platform.
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14464>
This reverts commit 2f0fbe06e6.
We don't handle the reconfiguration of existing HiZ surfaces, nor do we
do so for CCS surfaces. This code path is unused, so we remove it.
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14464>
The gfx7 MCS restriction for SINT formats actually applies to
multisampling in general. Place the stronger restriction in the format
support check and assert this in isl_surf_get_mcs_surf.
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14464>
The pitch check for 16x multisampled surfaces should already be covered
by the pitch_in_range check in isl_calc_row_pitch.
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14464>
Follow the CCS and MCS functions by returning false for unsupported
cases. This reduces the burden on the caller.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14091>
The new HiZ compresses twice as many rows of the depth surface compared
to TGL (Bspec 47009). Also, its tiling needs to be specified in
3DSTATE_HIER_DEPTH_BUFFER_BODY::TiledMode.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14091>
An 8x4 HiZ block doesn't fit in with the new formulas for sizing HiZ on
XeHP. Update a comment which assumed this block size on SKL+.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14091>
* Check the format's compression type instead of the format directly to
prepare for a new HiZ format on XeHP.
* Adjust the gfx12+ calculations so that XeHP will automatically be
handled.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14091>
The MOCS entry used for this on Tigerlake doesn't exist on DG2.
Ref: aca31baafc ("isl: Enable Tigerlake HDC:L1 caches via MOCS in various cases.")
Suggested-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14467>
The comment states that 64K alignment of surfaces is required when an
aux map is present on the platform. However, the code checks for GFX12
instead of dev->info->has_aux_map. Update the code to match the comment.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13555>
These checks are done in isl_format_supports_ccs_*. Since
isl_surf_supports_ccs calls these functions, it doesn't need to check
them itself.
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14082>
These formats are used when creating surfaces with the
I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS modifier.
Makes iris pass the out-of-tree piglit test,
ext_image_dma_buf_import-intel-modifiers.
Fixes: 1433fe7860 ("intel/isl: Unify fmt checks in isl_surf_supports_ccs")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14082>
On XeHP, the XY_BLOCK_COPY_BLT command has a number of fields that
describe the layout of the surface, much like SURFACE_STATE does.
Several of them are encoded in such a similar manner that we really
would like to reuse the isl helpers for emitting those. This commit
moves them into a new isl_genX_helpers.h file which I can include
from the BLORP code. (The alternative would be to add XY_BLOCK_COPY_BLT
filling commands to isl, but that...seems more like a BLORP feature.)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14094>
On TGL+, require that the surface format supports CCS_E in order to
support CCS. This aligns with the ISL code that pads the primary
surface for CCS on this platform.
Pre-TGL, require support for either CCS_D or CCS_E.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12398>
The sampler can only decode ASTC surfaces that are Y-tiled. ISL has
been asserting this restriction at surface creation time.
However, some drivers want to create a surface that is only used for
copying compressed data. And during the copy, the surface won't have a
compressed format.
To enable this behavior, we choose to move the tiling assertion to the
moment a surface state is created for the sampler.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13881>
We'd like to add safeguards against accidental use of MOCS 0 (uncached),
which can have large performance implications. One case where we use
MOCS of 0 is SURFTYPE_NULL depth, stencil, and HiZ buffers, where MOCS
really shouldn't matter, as there's no actual surface to be cached.
That said, it should be harmless to set MOCS for these null surfaces.
We now set the one provided in info->mocs regardless of whether any
buffers actually exist or not.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
We'd like to add safeguards against accidental use of MOCS 0 (uncached),
which can have large performance implications. One case where we use
MOCS of 0 is SURFTYPE_NULL surfaces, where MOCS really shouldn't matter,
as there's no actual surface to be cached.
That said, it should be harmless to set MOCS for these null surfaces;
we can just assume a generic MOCS for internal buffers.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
With the `gtest` protocol meson will add some extra arguments to the
test to generate better junit results, which may be useful. This
protocol is only available in meson 0.55.0+, so keep using the default
`exitcode` protocol for meson older than that.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8484>
INTEL_DEBUG is defined (since 4015e1876a) as:
#define INTEL_DEBUG __builtin_expect(intel_debug, 0)
which unfortunately chops off upper 32 bits from intel_debug
on platforms where sizeof(long) != sizeof(uint64_t) because
__builtin_expect is defined only for the long type.
Fix this by changing the definition of INTEL_DEBUG to be function-like
macro with "flags" argument. New definition returns 0 or 1 when
any of the flags match.
Most of the changes in this commit were generated using:
for c in `git grep INTEL_DEBUG | grep "&" | grep -v i915 | awk -F: '{print $1}' | sort | uniq`; do
perl -pi -e "s/INTEL_DEBUG & ([A-Z0-9a-z_]+)/INTEL_DBG(\1)/" $c
perl -pi -e "s/INTEL_DEBUG & (\([A-Z0-9_ |]+\))/INTEL_DBG\1/" $c
done
but it didn't handle all cases and required minor cleanups (like removal
of round brackets which were not needed anymore).
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13334>
If the ISL caller didn't specify a row_pitch_B, let's use the
NVIDIA/AMD requirements. Otherwise keep using the Intel requirement,
as the caller is likely trying to import a buffer and if we can deal
with that row_pitch_B, we should accept it.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: a3a4517f41 ("isl: Work around NVIDIA and AMD display pitch requirements")
Reported-by: Dongwon Kim <dongwon.kim@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13024>
v2: cleanup (Jordan Justen)
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13241>
We do, however, leave a nice tombstone comment in case anyone comes
looking. Given the age and scarcity of Cherry View hardware and ASTC
apps that run on desktop Linux, it's unlikely we'll ever bother to
implement it.
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13206>
For compressed formats, filtering and sampling has always gone together.
This lets us avoid duplicating all those nasty special cases between the
two functions.
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13206>
Avoid using a sparse and relatively large array for HALIGN encoding.
Additionally, this provides validation of the input alignment values.
Suggested-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
We're going to start asserting for valid halign/valign values during
surface state emission. Pre-SKL, isl_surf_get_uncompressed_surf creates
uncompressed surfaces with invalid halign/valign values - 1x1. Fix this
by replacing the call to isl_surf_get_image_surf with isl_surf_init,
passing in the uncompressed format up-front.
As we're no longer using isl_surf_get_image_surf, we also need to get
the x and y offset of the image ourselves. Instead of getting a
sample-based offset, then converting to elements later on, we use
isl_surf_get_image_offset_B_tile_el to get the offset in elements
up-front.
With the above two changes, the generic code after the else-block is no
longer needed for the single-layer-view code path. We move it and
specialize it to the if-block (which is executed SKL+ and handles
multi-layer views).
Cc: mesa-stable
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
Try to avoid having to update isl_gfx6_filter_tiling when new tilings
are added for new platforms. Note that the allow-list uses
ISL_TILING_ANY_Y_MASK and thus assumes that no new Y-tilings will be
added in the future.
Suggested-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
In order to size Tile64 surfaces correctly, make sure that the total
physical extent is arrayed. The code should handle 3D surfaces as well,
but is untested for now.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
Implement the new XeHP alignment rules for surface layout.
RENDER_SURFACE_STATE objects still need updating, but that's left for a
separate commit.
Rework:
* Nanley: Include Sagar's VALIGN fix for D16_UNORM.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
