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isl: Don't enable HDC:L1 caches on DG2

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The MOCS entry used for this on Tigerlake doesn't exist on DG2.

Ref: aca31baafc ("isl: Enable Tigerlake HDC:L1 caches via MOCS in various cases.")
Suggested-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14467>
This commit is contained in:
Jordan Justen 2022-01-06 13:33:07 -08:00 • committed by Marge Bot
parent 67fc7a1763
commit 0fc93928f1
1 changed files with 1 additions and 1 deletions
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src/intel/isl/isl.c
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@ -170,7 +170,7 @@ isl_mocs(const struct isl_device *dev, isl_surf_usage_flags_t usage,
if (external)
return dev->mocs.external;
if (dev->info->ver >= 12 && dev->info->platform != INTEL_PLATFORM_DG1) {
if (dev->info->verx10 == 120 && dev->info->platform != INTEL_PLATFORM_DG1) {
if (usage & ISL_SURF_USAGE_STAGING_BIT)
return dev->mocs.internal;