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intel/isl: Require Y-tiling for depth on gfx4-5

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This enables isl_surf_get_hiz_surf to be simplified.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14091>
This commit is contained in:
Nanley Chery 2021-12-08 13:28:46 -05:00 • committed by Marge Bot
parent 267689a269
commit 50967402cc
1 changed files with 3 additions and 3 deletions
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6
src/intel/isl/isl_gfx4.c
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@ -56,10 +56,10 @@ isl_gfx4_filter_tiling(const struct isl_device *dev,
* BWT014 The Depth Buffer Must be Tiled, it cannot be linear. This
* field must be set to 1 on DevBW-A. [DevBW -A,B]
*
* In testing, the linear configuration doesn't seem to work on gfx4.
* In testing, the linear configuration doesn't seem to work on I965. We
* choose to be consistent and require tiling for gfx4-5.
*/
*flags &= (ISL_GFX_VER(dev) == 4 && !ISL_DEV_IS_G4X(dev)) ?
ISL_TILING_Y0_BIT : (ISL_TILING_Y0_BIT | ISL_TILING_LINEAR_BIT);
*flags &= ISL_TILING_Y0_BIT;
}
if (info->usage & ISL_SURF_USAGE_DISPLAY_BIT) {