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intel/isl: Use a new HiZ format on XeHP+

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The new HiZ compresses twice as many rows of the depth surface compared
to TGL (Bspec 47009). Also, its tiling needs to be specified in
3DSTATE_HIER_DEPTH_BUFFER_BODY::TiledMode.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14091>
This commit is contained in:
Nanley Chery 2021-12-05 22:29:44 -05:00 • committed by Marge Bot
parent 7d0e847856
commit 267689a269
5 changed files with 40 additions and 7 deletions
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15
src/intel/isl/isl.c
View file

@ -465,9 +465,9 @@ isl_tiling_get_info(enum isl_tiling tiling,
break;
case ISL_TILING_HIZ:
/* HiZ buffers are required to have ISL_FORMAT_HIZ which is an 8x4
* 128bpb format. The tiling has the same physical dimensions as
* Y-tiling but actually has two HiZ columns per Y-tiled column.
/* HiZ buffers are required to have a 128bpb HiZ format. The tiling has
* the same physical dimensions as Y-tiling but actually has two HiZ
* columns per Y-tiled column.
*/
assert(bs == 16);
logical_el = isl_extent4d(16, 16, 1, 1);
@ -591,7 +591,7 @@ isl_surf_choose_tiling(const struct isl_device *dev,
/* HiZ surfaces always use the HiZ tiling */
if (info->usage & ISL_SURF_USAGE_HIZ_BIT) {
assert(info->format == ISL_FORMAT_HIZ);
assert(isl_format_is_hiz(info->format));
assert(tiling_flags == ISL_TILING_HIZ_BIT);
*tiling = isl_tiling_flag_to_enum(tiling_flags);
return true;
@ -2043,9 +2043,12 @@ isl_surf_get_hiz_surf(const struct isl_device *dev,
*/
const unsigned samples = ISL_GFX_VER(dev) >= 9 ? 1 : surf->samples;
const enum isl_format format =
ISL_GFX_VERX10(dev) >= 125 ? ISL_FORMAT_GFX125_HIZ : ISL_FORMAT_HIZ;
return isl_surf_init(dev, hiz_surf,
.dim = surf->dim,
.format = ISL_FORMAT_HIZ,
.format = format,
.width = surf->logical_level0_px.width,
.height = surf->logical_level0_px.height,
.depth = surf->logical_level0_px.depth,
@ -2172,7 +2175,7 @@ isl_surf_supports_ccs(const struct isl_device *dev,
assert(hiz_surf->usage & ISL_SURF_USAGE_HIZ_BIT);
assert(hiz_surf->tiling == ISL_TILING_HIZ);
assert(hiz_surf->format == ISL_FORMAT_HIZ);
assert(isl_format_is_hiz(hiz_surf->format));
} else if (surf->samples > 1) {
const struct isl_surf *mcs_surf = hiz_or_mcs_surf;

9
src/intel/isl/isl.h
View file

@ -385,6 +385,7 @@ enum isl_format {
/* Formats for auxiliary surfaces */
ISL_FORMAT_HIZ,
ISL_FORMAT_GFX125_HIZ,
ISL_FORMAT_MCS_2X,
ISL_FORMAT_MCS_4X,
ISL_FORMAT_MCS_8X,
@ -1900,6 +1901,14 @@ isl_format_is_mcs(enum isl_format fmt)
return fmtl->txc == ISL_TXC_MCS;
}
static inline bool
isl_format_is_hiz(enum isl_format fmt)
{
const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
return fmtl->txc == ISL_TXC_HIZ;
}
static inline bool
isl_format_is_planar(enum isl_format fmt)
{

19
src/intel/isl/isl_emit_depth_stencil.c
View file

@ -233,7 +233,24 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch,
hiz.SurfacePitch = info->hiz_surf->row_pitch_B - 1;
#if GFX_VERx10 >= 125
hiz.TiledMode = isl_encode_tiling[info->hiz_surf->tiling];
/* From 3DSTATE_HIER_DEPTH_BUFFER_BODY::TiledMode,
*
* HZ buffer only supports Tile4 mode
*
* and from Bspec 47009, "Hierarchical Depth Buffer",
*
* The format of the data in the hierarchical depth buffer is not
* documented here, as this surface needs only to be allocated by
* software.
*
* We choose to apply the second quote to the first. ISL describes HiZ
* with a tiling that has the same extent as Tile4 (128Bx32), but a
* different internal layout. This has two benefits: 1) it allows us to
* have the correct allocation size and 2) we can continue to use a
* tiling that was determined to exist on some prior platforms.
*/
assert(info->hiz_surf->tiling == ISL_TILING_HIZ);
hiz.TiledMode = TILE4;
#endif
#if GFX_VER >= 12

1
src/intel/isl/isl_format_layout.csv
View file

@ -333,6 +333,7 @@ ASTC_HDR_2D_10X10_FLT16 , 128, 10, 10, 1, sf16, sf16, sf16, sf16, ,
ASTC_HDR_2D_12X10_FLT16 , 128, 12, 10, 1, sf16, sf16, sf16, sf16, , , , , linear, astc
ASTC_HDR_2D_12X12_FLT16 , 128, 12, 12, 1, sf16, sf16, sf16, sf16, , , , , linear, astc
HIZ , 128, 8, 4, 1, , , , , , , , , , hiz
GFX125_HIZ , 128, 8, 8, 1, , , , , , , , , , hiz
MCS_2X , 8, 1, 1, 1, , , , , , , , , , mcs
MCS_4X , 8, 1, 1, 1, , , , , , , , , , mcs
MCS_8X , 32, 1, 1, 1, , , , , , , , , , mcs

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3
src/intel/isl/isl_gfx12.c
View file

@ -91,6 +91,9 @@ isl_gfx125_choose_image_alignment_el(const struct isl_device *dev,
enum isl_msaa_layout msaa_layout,
struct isl_extent3d *image_align_el)
{
/* Handled by isl_choose_image_alignment_el */
assert(info->format != ISL_FORMAT_GFX125_HIZ);
const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
if (tiling == ISL_TILING_64) {