Commit graph

178351 commits

Author SHA1 Message Date
Timothy Arceri
2e7514cfa8 glsl: remove now unused varying linker code
All of this varying linking code has now been ported to the NIR linker.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25371>
2023-09-28 13:55:16 +00:00
Timothy Arceri
36e49c162c glsl: switch to nir linkers cross_validate_outputs_to_inputs()
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25371>
2023-09-28 13:55:16 +00:00
Timothy Arceri
7d1948e9b5 glsl: implement cross_validate_outputs_to_inputs() in nir linker
This is mostly a direct port of the GLSL IR code there are only
2 real functional changes.

1. The direct use of mesa symbol_table instead of glsl_symbol_table.
   However since none of the extra functionality offered by
   glsl_symbol_table was ever used here this can be seen as an
   improvement.

2. Because interface blocks are lowered before this new nir linker
   sees them we must explicitly skip them (they are validated
   elsewhere) to avoid errors.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25371>
2023-09-28 13:55:16 +00:00
Timothy Arceri
f2e87c5c28 nir: add used field to nir variables
Will be use in a following path by the glsl nir based linker.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25371>
2023-09-28 13:55:16 +00:00
Timothy Arceri
0bfae24640 glsl: move is_gl_identifier() to linker_util
This had started to multiply around the NIR linker. Here we move it to a
common helper shared by GLSL IR and NIR.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25371>
2023-09-28 13:55:16 +00:00
Timothy Arceri
78b9f1053f glsl: move interpolation_string() to linker_util
Moving it here allows us to use in in the NIR linker too.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25371>
2023-09-28 13:55:16 +00:00
Timothy Arceri
337c32cb3a nir: copy explicit_invariant flag to nir vars
This will be used in the following patch.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25371>
2023-09-28 13:55:16 +00:00
Samuel Pitoiset
af2a96bb37 radv: stop skip emitting CB states when there is no color attachment
This is actually wrong. For example, if there is a DCC decompress
draw followed by a draw without any color attachments,
CB_COLOR_CONTROL.MODE is still CB_DCC_DECOMPRESS but it should be
CB_DISABLED. For some reasons, this hangs on RDNA3 (VM faults are also
reported through dmesg).

This fixes GPU hangs with Resident Evil 6, Star Wars The Old Republic
and probably more games on RDNA3.

Strictly speaking, I don't think this dynamic state optimization is
worth a try, even for other states, and I think it would be safer to
remove it completely.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9335
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8327
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9878
Fixes: c08082e861 ("radv: ignore all CB dynamic states when there is no color attachments")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25402>
2023-09-28 13:32:35 +00:00
Mike Blumenkrantz
441e57048b glx: XFree visual info
cc: mesa-stable

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25441>
2023-09-28 12:17:49 +00:00
Cong Liu
02150ca017 r300: Fix out-of-bounds access in ntr_emit_store_output()
This patch resolves the problem by modifying the for loop condition
to ensure that it stays within the bounds of the array (i.e., i < 4)

Signed-off-by: Cong Liu <liucong2@kylinos.cn>
Reviewed-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25419>
2023-09-28 09:51:38 +00:00
Eric Engestrom
9bc1fd25a4 ci/zink+radv: document flake
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25427>
2023-09-28 09:06:59 +00:00
Christian Gmeiner
435699de77 isaspec: python does not need ';'
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25437>
2023-09-28 08:15:50 +00:00
Ian Romanick
03c1e67b6c spirv: Track when a shader has a cooperative matrix
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23825>
2023-09-28 07:35:02 +00:00
Caio Oliveira
b98f87612b spirv: Implement SPV_KHR_cooperative_matrix
Includes a modified version of using extract/insert for OpLoad/OpStore
from Ian.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (earlier version)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> (earlier version)
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23825>
2023-09-28 07:35:02 +00:00
Caio Oliveira
b17a2c35bc spirv: Let vtn_ssa_value hold references to variables
In certain cases, we have complex opaque objects that are loaded
into (SPIR-V) SSA values.  To represent these, we now can store a
reference to a variable in vtn_ssa_value.

Also implements a few operations we know will have to be supported,
like Select and Copy.

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23825>
2023-09-28 07:35:02 +00:00
Caio Oliveira
3d7e5ec758 spirv: Expose some memory related functions in vtn_private.h
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23825>
2023-09-28 07:35:02 +00:00
Caio Oliveira
af3eb80afa nir: Handle cooperative matrix in various passes
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23825>
2023-09-28 07:35:02 +00:00
Caio Oliveira
3105d516d0 nir: Add new intrinsics for Cooperative Matrix
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23825>
2023-09-28 07:35:02 +00:00
Caio Oliveira
2d0f4f2c17 compiler/types: Add support for Cooperative Matrix types
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23825>
2023-09-28 07:35:02 +00:00
Paulo Zanoni
b75da97a1d anv: enable sparse resources by default
This of course only applies to xe.ko. There is no reason to keep it
disabled by default.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23045>
2023-09-28 06:16:40 +00:00
Paulo Zanoni
7e2d8cced3 anv/sparse: add INTEL_DEBUG=sparse
This pollutes stderr a lot, but I've used it countless times while
developing this code.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23045>
2023-09-28 06:16:40 +00:00
Paulo Zanoni
2bdd01187d anv/sparse: get ready to issue a single vm_bind ioctl per non-opaque bind
Game testing shows it's common for this operation to result in
multiple bind regions, so try to use a single ioctl when we can.

Actual testing reveals 136 shader-related tests fail when we actually
do this, so for now keep doing a single bind per ioctl while leaving a
very easy way to the desired behavior when we figure this out.

It should also be possible to go even higher-level and do this at the
anv_queue_submit_sparse_bind_locked() layer, but that should happen in
future commits.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23045>
2023-09-28 06:16:40 +00:00
Paulo Zanoni
6368c1445f anv/sparse: add the initial code for Sparse Resources
This giant patch implements a huge chunk of the Vulkan Sparse
Resources API. I previously had this as a nice series of many smaller
patches that evolved as the xe.ko added more features, but once I was
asked to squash some of the major reworks I realized I wouldn't be
able easily rewrite history, so I just squased basically the whole
series into a giant patch. I may end up splitting this again later if
I find a way to properly do it.

If we want to support the DX12 API through vkd3d we need to support
part of the the Sparse Resources API. If we don't, a bunch of Steam
games won't work.

For now we only support the xe.ko backend, but the vast majority of
the code is KMD-independent and so an i915.ko implementation would use
most of what's here, just extending the part that binds and unbinds
memory.

v2+: There's no way to sanely track the version history of this patch
in this commit message. Please refer to Gitlab.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23045>
2023-09-28 06:16:40 +00:00
Paulo Zanoni
e4598f0eea intel/isl: simplify the check for maximum surface size
The only thing that changes between these 3 checks is the size.

This entire patch was suggested by Kenneth Graunke, I just converted
his gitlab comment to a git commit.

Credits-to: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23045>
2023-09-28 06:16:40 +00:00
Paulo Zanoni
0de5d142e8 intel/isl: add ISL_SURF_USAGE_SPARSE_BIT
Vulkan Sparse resources have their own set of rules, so here we try to
make ISL aware of them through ISL_SURF_USAGE_SPARSE_BIT.

The big deal here is when some image ends up not using Tile64 nor
TileYs. Previously Ys was not supported on TGL at all, and Tile64 did
not have support for 3D. Now we still have some formats that end up
not being used with either Tile64 and Ys, but need to support Sparse
on them (e.g., YUV on Tile64). In the future we may have new tiling
formats or hardware restrictions that would force this case to happen
again.

So here we do some adjustments so we can make sparse work with other
tiling formats, although with limited functionality (e.g., those
formats may be restricted to opaque binds, and certainly don't support
the standard block shapes).

v2: before we had Ys support, we had defined TGL's block size as 4k.
v3: move the size_B chunk to before nte notify_failure() checks (Ken).

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23045>
2023-09-28 06:16:40 +00:00
Faith Ekstrand
968cefbff1 nvk: Cache NIR shaders
We can't cache shader binaries just yet but this at least lets us cache
the output of spirv_to_nir and the initial optimize.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25443>
2023-09-28 03:55:53 +00:00
Faith Ekstrand
cdbd86c176 nvk: Add a default pipeline cache
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25443>
2023-09-28 03:55:53 +00:00
Faith Ekstrand
abe52a6d03 nvk: Re-structure early shader compilation a bit
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25443>
2023-09-28 03:55:53 +00:00
Faith Ekstrand
a4f8fd9dd5 nvk: Hook up the disk cache
This won't actually do much yet because we don't have pipeline caches
yet but it turns on the infrastructure.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25443>
2023-09-28 03:55:53 +00:00
Faith Ekstrand
d08df319ca nvk: Store a 20-bit driver_build_sha in nvk_instance
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25443>
2023-09-28 03:55:53 +00:00
Timothy Arceri
1780102923 nir: fix typo in comment
The variable is unused or dead, not used.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25414>
2023-09-28 01:54:43 +00:00
antonino
76d150674b vulkan: Handle vkSetDebugUtilsObjectNameEXT on WSI objects
Some WSI objects don't extend `vk_object_base` therefore they need
special handling.

Fixes: 3c87618d35 ("vulkan: Handle vkGet/SetPrivateDataEXT on Android swapchains")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24752>
2023-09-28 01:23:55 +00:00
antonino
5fe289d741 vulkan: Extend vkGet/SetPrivateDataEXT handling to VkSurface
VkSurface is handled by WSI and it doesn't extend `vk_object_base` so it
needs special handling.

Fixes: 3c87618d35 ("vulkan: Handle vkGet/SetPrivateDataEXT on Android swapchains")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24752>
2023-09-28 01:23:55 +00:00
antonino
710d478066 vulkan: Extend vkGet/SetPrivateDataEXT handling to all platforms
Non-android platforms use mesa WSI, however some WSI object still don't
extend `vk_object_base` so they still need special handling.

Fixes: 3c87618d35 ("vulkan: Handle vkGet/SetPrivateDataEXT on Android swapchains")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24752>
2023-09-28 01:23:55 +00:00
Dave Airlie
c45ae052f0 llvmpipe/cs: migrate cs image handle to common jit code.
This moves some of the code over, and uses the generic paths.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25416>
2023-09-28 00:41:04 +00:00
Dave Airlie
2c74f825f4 llvmpipe/cs: migrate to generic jit texture from pipe code.
This moves some cs specific bits to the generic code and uses it.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25416>
2023-09-28 00:41:04 +00:00
Marcin Ślusarz
ea92bd8d44 intel/compiler: mask GS URB handles at thread payload construction
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
2023-09-27 23:57:25 +00:00
Marcin Ślusarz
815eee10e0 intel/compiler/mesh: implement IO for xe2
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
2023-09-27 23:57:25 +00:00
Marcin Ślusarz
ee4214de6e intel/compiler/mesh: fix position of output URB handle for xe2
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
2023-09-27 23:57:25 +00:00
Francisco Jerez
7f3dc4505d intel/fs: Delete manual 'inst->mlen' calculations from all uses of logical URB reads.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
2023-09-27 23:57:25 +00:00
Francisco Jerez
53d1d793cb intel/fs: Delete manual 'inst->mlen' calculations from all uses of logical URB writes.
Rework:
 * Marcin: update emit_urb_indirect_vec4_write

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
2023-09-27 23:57:25 +00:00
Francisco Jerez
34a2c9ce35 intel/fs: Specify number of data components of logical URB writes via control immediate.
This is what most logical SEND messages do when they take a variable
number of components.  'inst->mlen' is expected to be zero for logical
SEND opcodes, which are expected to behave like plain arithmetic
operations, so certain automated transformations (like SIMD lowering)
can manipulate them without opcode-specific special-casing.

Guessing the number of components from 'inst->mlen' has other
disadvantages, because it requires duplicating the logic that infers
the message payload size in every use of the instruction -- Instead we
can just do the computation once during logical send lowering.  In
addition on LNL platform this causes the 'inst->mlen' field of URB
writes to have units inconsistent with every other SEND instruction,
which is likely to lead to confusion and bugs down the road.

Rework:
 * Marcin: update emit_urb_indirect_vec4_write

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
2023-09-27 23:57:25 +00:00
Francisco Jerez
74c9973c0b intel/fs/xe2+: Fix URB writes with 0 data components.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
2023-09-27 23:57:25 +00:00
Caio Oliveira
c89597085a intel/compiler/xe2: Update TCS ICP handle code to support SIMD16
Rework:
 * Use ffs(grf_size_bytes) (s-b Ken)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
2023-09-27 23:57:25 +00:00
Caio Oliveira
f0fcb778b4 intel/compiler/xe2: Fix URB writes in TCS
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
2023-09-27 23:57:25 +00:00
Caio Oliveira
0c03018abf intel/compiler/xe2: URB fence uses LSC now
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
2023-09-27 23:57:25 +00:00
Ian Romanick
623465e26d intel/compiler/xe2: Update fs_visitor::emit_urb_writes to not assume SIMD8
v2: Account for 512b physical registers which causes the URB handle to be in FIXED_GFR 2 instead of 1.

XXX - Use fs_builder::vgrf() instead of open-coded dispatch_width calculations.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
2023-09-27 23:57:25 +00:00
Kenneth Graunke
4fffdbbfa2 intel/fs: Fix Xe2 URB read/lowering with per-slot offsets
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
2023-09-27 23:57:25 +00:00
Jordan Justen
c28539a2fe intel/compiler: Use enum xe2_lsc_cache_load on xe2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
2023-09-27 23:57:25 +00:00
Jordan Justen
8d27b327f2 intel/compiler: Add enum xe2_lsc_cache_load
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
2023-09-27 23:57:25 +00:00