Commit graph

72806 commits

Author SHA1 Message Date
Jason Ekstrand
2b2f1f16a0 nir/lower_vec_to_movs: Get rid of start_idx and swizzle compacting
Previously, we did this thing with keeping track of a separate start_idx
which was different from the iteration variable.  I think this was a relic
of the way that GLSL IR implements writemasks.  In NIR, if a given bit in
the writemask is unset then that channel is just "unused", not missing.  In
particular, a vec4 operation with a writemask of 0xd will use sources 0, 2,
and 3 and leave source 1 alone.  We can simplify things a good deal (and
make them correct) by removing this "compacting" step.

Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2015-09-15 11:13:48 -07:00
Jason Ekstrand
c951bb8305 i965/vec4_nir: Use partial SSA form rather than full non-SSA
We made this switch in the FS backend some time ago and it seems to make a
number of things a bit easier.  In particular, supporting SSA values takes
very little work in the backend and allows us to take advantage of the
majority of the SSA information even after we've gotten rid of Phi nodes.

Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
2015-09-15 11:13:48 -07:00
Jason Ekstrand
c3f8cde964 nir/lower_vec_to_movs: Handle partially SSA shaders
v2 (Jason Ekstrand):
 - Use nir_instr_rewrite_dest
 - Pass the impl directly into lower_vec_to_movs_block

Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
2015-09-15 11:13:45 -07:00
Jason Ekstrand
b7eeced3c7 nir/lower_vec_to_movs: Pass the shader around directly
Previously, we were passing the shader around, we were just calling it
"mem_ctx".  However, the nir_shader is (and must be for the purposes of
mark-and-sweep) the mem_ctx so we might as well pass it around explicitly.

Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
2015-09-15 11:13:40 -07:00
Jason Ekstrand
cadd7dd384 i965/fs: Add a very basic validation pass
Currently the validation pass only validates that regs_read and
regs_written are consistent with the sizes of VGRF's.  We can add more as
we find it to be useful.

Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-09-15 11:11:50 -07:00
Jason Ekstrand
0c6df7a1cb i965/fs_surface_builder: Only apply predicate to components that exist
In certain conditions, we have to do bounds-checking in the shader for
image_load_store.  The way this works for image loads is that we do a
predicated load and then emit a series of selects, one per component,
that gives us 0 or the loaded value depending on whether or not you're
in bounds.  However, we were hard-coding 4 components which may not be
correct.  Instead, we should be using size which is the number of
components read.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2015-09-15 11:09:48 -07:00
Jason Ekstrand
5182400054 i965/fs: Only read output_components many components when writing an output
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
2015-09-15 11:08:12 -07:00
Jason Ekstrand
f55836f567 i965/fs: Set output_components for lowered clip distance outputs
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
2015-09-15 11:07:54 -07:00
Nanley Chery
8200793649 mesa/teximage: restrict GL_ETC1_RGB8_OES support to GLES
According to the extensions table and our glext headers,
OES_compressed_ETC1_RGB8_texture is only supported in
GLES1 and GLES2. Since we may give users a GLES3 context
when a GLES2 context is requested, we also allow this
extension for GLES3 as well.

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
2015-09-15 10:11:14 -07:00
Nanley Chery
48961fa3ba mesa/extensions: restrict GL_OES_EGL_image to GLES
Driver vendors do this as well. The extension specification
lists GLES 1.1 or 2.0 as requirements.

Reviewed-by: Chad Versace <chad.versace@intel.com>
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
2015-09-15 10:00:00 -07:00
Nanley Chery
fe796a1831 mesa/extensions: restrict luminance alpha formats to API_OPENGL_COMPAT
According the GL 3.1 spec, luminance alpha formats are deprecated.

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
2015-09-15 10:00:00 -07:00
Thomas Hellstrom
edfb7ed109 gallium/svga: Enable PIPE_FORMAT_L8_UNORM for vgpu10
It's extensively used by XA for a8- and planar yuv component surfaces.
This fixes broken XA yuv blits using vgpu10 contexts.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2015-09-15 09:25:02 -07:00
Emil Velikov
a1ac742f70 egl/dri2: don't leak the fd on dri2_terminate
Currently the check was incorrect as it did not consider the (unlikely)
case of fd == 0. In order to fix this we should first correctly
initialize it to -1, as the swrast implementations leave it set to zero
(props to calloc()).

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Boyan Ding <boyan.j.ding@gmail.com>
2015-09-15 12:39:02 +01:00
Emil Velikov
bd5bcb5b8c egl/dri2/drm: compact existing device mgmt
Move the fcntl(dupfd_cloexec) to the else branch where it belongs.
Otherwise it's not immediately obvious that the code is hit, only when
an existing device is used.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Boyan Ding <boyan.j.ding@gmail.com>
2015-09-15 12:37:27 +01:00
Matt Turner
e4f0d26c8c egl/dri2: Close file descriptor on error.
v2: [Emil Velikov]
Rework the error path to a common goto, close only if we own the fd.
v3; [Emil Velikov]
Always close the fd (we either opened the device or dup'd) (Boyan, Ian)

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Boyan Ding <boyan.j.ding@gmail.com>
2015-09-15 12:37:26 +01:00
Ray Strode
4bf151e662 gbm: convert gbm bo format to fourcc format on dma-buf import
At the moment if a gbm buffer is imported and the gbm buffer
has an old-style GBM_BO_FORMAT format, the import will crash,
since it's passed directly to DRI functions that expect
a fourcc format (as provided by the newer GBM_FORMAT
definitions)

This commit addresses the problem in two ways:

1) it prevents invalid formats from leading to a crash by
returning EINVAL if the image couldn't be created

2) it translates GBM_BO_FORMAT formats into the comparable
GBM_FORMAT formats.

Reference: https://bugzilla.gnome.org/show_bug.cgi?id=753531
CC: "10.6 11.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
2015-09-15 12:27:45 +01:00
Alejandro Piñeiro
a26e82b81d docs: document INTEL_DEBUG 'optimizer' envvar
Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-09-15 08:33:35 +02:00
Kristian Høgsberg Kristensen
a548c75e31 i965: Move perf_debug code to brw_codegen_*_prog()
We're trying to avoid a libdrm dependency in the core compiler, so let's
move the perf_debug code one level up from the brw_*_emit() helpers to
the brw_codegen_*_prog() helpers.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: Kristian Høgsberg Kristensen <krh@bitplanet.net>
2015-09-14 16:56:59 -07:00
Kristian Høgsberg Kristensen
84f2ed2cfd i965: Move brw_fs_precompile() to brw_wm.c
All other precompile functions live in the brw_<stage>.c files, make fs
follow the convention.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: Kristian Høgsberg Kristensen <krh@bitplanet.net>
2015-09-14 16:55:49 -07:00
Kristian Høgsberg Kristensen
dc70c86b9b i965: Move compute shader code around
This moves the compute shader code around in order to make the way the
code is split up more consistent. There should be no functional changes.
Typically we have a few files per stage:

    brw_vs.c, brw_wm.c brw_gs.c:

        code to drive code generation and implement precompiling and
        cache search.

    genX_<stage>_state.c

        gen specific implementation of the state emission for the shader
        stage.

The brw_*_emit() functions are all in the same files as the visitor
classes they use (with the exception of VS, which may use either vec4 or
fs).

To make compute follow this convention, we move the brw_cs_emit()
function into brw_fs.cpp. We can then rename brw_cs.cpp to brw_cs.c and
do this in C like the other similar files.  Finally, move state setup
and atoms to gen7_cs_state.c.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: Kristian Høgsberg Kristensen <krh@bitplanet.net>
2015-09-14 16:52:42 -07:00
Anuj Phogat
64e25167ed meta: Abort meta pbo path if TexSubImage need signed unsigned conversion
See similar fix for Readpixels in mesa commit 0d20790. Jason suggested
we need that for TexSubImage as well.

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2015-09-14 15:22:37 -07:00
Ilia Mirkin
5877a594d5 nvc0/ir: start offset at texBindBase for txq, like regular texturing
Curiously this has no actual effect. I think it's because the first 8
textures are bound in multiple slots for some reason. However seems
prudent to use these the same way as regular texturing, esp in the case
where there are more than 8 textures bound.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-09-14 17:26:25 -04:00
Eric Anholt
64aee8fe9f vc4: Fix build from recent NIR cleanups. 2015-09-14 11:21:07 -04:00
Antia Puentes
b8d2263c83 i965/vec4_nir: Load constants as integers
Loads constants using integer as their register type, like it is
done in FS backend.

No shader-db changes in HSW.

Cc: "10.6 11.0" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91716
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2015-09-14 12:11:46 +02:00
Antia Puentes
79f1a7ae28 i965/vec4: Fix saturation errors when coalescing registers
If the register types do not match and the instruction
that contains the final destination is saturated, register
coalescing generated non-equivalent code.

This did not happen when using IR because types usually
matched, but it is visible in nir-vec4.

For example,
   mov      vgrf7:D vgrf2:D
   mov.sat  m4:F vgrf7:F

is coalesced to:
   mov.sat  m4:D vgrf2:D

The patch prevents coalescing in such scenario, unless the
instruction we want to coalesce into is a MOV (without type
conversion implied). In that case, the patch sets the register
types to the type of the final destination.

Shader-db results in HSW (only vec4 instructions shown):

total instructions in shared programs: 1754415 -> 1754416 (0.00%)
instructions in affected programs:     74 -> 75 (1.35%)
helped:                                0
HURT:                                  1
GAINED:                                0
LOST:                                  0

Only one extra instruction in one of the shaders, that comes from
eliminating a saturation error by preventing register coalesce.

Cc: "10.6 11.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2015-09-14 12:11:46 +02:00
Tapani Pälli
d1bce52e13 docs: cleanups + mark some work as done
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-09-14 09:29:30 +03:00
Ilia Mirkin
f0b9d53262 docs: only astc ldr required for ES3.2, not hdr
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2015-09-14 02:08:42 -04:00
Ilia Mirkin
67d2d3ba43 st/mesa: emit TXQS, support ARB_shader_texture_image_samples
The image component of the ext is a no-op since there is no image support
in gallium (yet).

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2015-09-13 18:24:45 -04:00
Ilia Mirkin
ec3fe42b3a r600g: add support for TXQS tgsi opcode
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>
2015-09-13 18:24:44 -04:00
Ilia Mirkin
4294db90b1 nv50/ir: add support for TXQS tgsi opcode
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-09-13 18:24:44 -04:00
Ilia Mirkin
f46a53ffa5 gallium: add PIPE_CAP_TGSI_TXQS to let st know if TXQS is supported
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>
2015-09-13 18:24:37 -04:00
Ilia Mirkin
d173c5e77d tgsi: add a TXQS opcode to retrieve the number of texture samples
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-09-13 18:24:01 -04:00
Jordan Justen
c4cf824658 glsl/cs: Initialize gl_LocalInvocationIndex in main()
We initialize gl_LocalInvocationIndex based on the extension spec
formula:

    gl_LocalInvocationIndex =
        gl_LocalInvocationID.z * gl_WorkGroupSize.x * gl_WorkGroupSize.y +
        gl_LocalInvocationID.y * gl_WorkGroupSize.x +
        gl_LocalInvocationID.x;

https://www.opengl.org/registry/specs/ARB/compute_shader.txt

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2015-09-13 09:53:17 -07:00
Jordan Justen
6823e12d5a glsl/cs: Exclude gl_LocalInvocationIndex from builtin variable stripping
We lower gl_LocalInvocationIndex based on the extension spec formula:

    gl_LocalInvocationIndex =
        gl_LocalInvocationID.z * gl_WorkGroupSize.x * gl_WorkGroupSize.y +
        gl_LocalInvocationID.y * gl_WorkGroupSize.x +
        gl_LocalInvocationID.x;

https://www.opengl.org/registry/specs/ARB/compute_shader.txt

We need to set this variable in main(), even if gl_LocalInvocationIndex
is not referenced by the shader. (It may be used by a linked shader.)
Therefore, we can't eliminate it as a dead variable.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2015-09-13 09:53:16 -07:00
Jordan Justen
2b6cc0395b glsl/cs: Initialize gl_GlobalInvocationID in main()
We initialize gl_GlobalInvocationID based on the extension spec
formula:

    gl_GlobalInvocationID =
        gl_WorkGroupID * gl_WorkGroupSize + gl_LocalInvocationID

https://www.opengl.org/registry/specs/ARB/compute_shader.txt

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2015-09-13 09:53:16 -07:00
Jordan Justen
c4d049f646 glsl: Move link_get_main_function_signature to a common location
Also rename to _mesa_get_main_function_signature.

We will call it near the end of compilation to insert some code into
main for initializing some compute shader global variables.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
2015-09-13 09:53:16 -07:00
Jordan Justen
34e187ec38 glsl/cs: Don't strip gl_GlobalInvocationID and dependencies
We lower gl_GlobalInvocationID based on the extension spec formula:

    gl_GlobalInvocationID =
        gl_WorkGroupID * gl_WorkGroupSize + gl_LocalInvocationID

https://www.opengl.org/registry/specs/ARB/compute_shader.txt

We need to set this variable in main(), even if gl_GlobalInvocationID
is not referenced by the shader. (It may be used by a linked shader.)
Therefore, we can't eliminate these as dead variables.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2015-09-13 09:53:16 -07:00
Jordan Justen
c5743a5d7f i965/nir: Support gl_WorkGroupID variable
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
2015-09-13 09:53:16 -07:00
Jordan Justen
4e454cb7c6 i965/cs: Initialize gl_WorkGroupID variable from payload
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
2015-09-13 09:53:16 -07:00
Jordan Justen
4f178f0d8b nir: Add gl_WorkGroupID system variable
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
2015-09-13 09:53:16 -07:00
Jordan Justen
f5bb5a1bf1 glsl/cs: Add gl_WorkGroupID variable
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
2015-09-13 09:53:16 -07:00
Jordan Justen
49f999b9cb i965/nir: Support gl_LocalInvocationID variable
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
2015-09-13 09:53:16 -07:00
Jordan Justen
43624361df i965/cs: Initialize gl_LocalInvocationID from payload
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
2015-09-13 09:53:16 -07:00
Jordan Justen
b94b57f7c5 i965/cs: Initialize gl_LocalInvocationID in push constant data
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
2015-09-13 09:53:16 -07:00
Jordan Justen
c7161a3c35 i965/cs: Reserve local invocation id in payload regs
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2015-09-13 09:53:16 -07:00
Jordan Justen
62e011d593 nir: Add gl_LocalInvocationID variable
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
2015-09-13 09:53:16 -07:00
Jordan Justen
bf8d6e501c glsl/cs: Add gl_LocalInvocationID variable
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
2015-09-13 09:53:16 -07:00
Krzesimir Nowak
08ceb5e076 softpipe: Change faces type to uint
This is to avoid needless float<->int conversions, since all
face-related computations are made on integers. Spotted by Emil
Velikov.

Reviewed-by: Brian Paul <brianp@vmware.com>
2015-09-13 09:50:21 -06:00
Rob Clark
59519c2283 freedreno/ir3: fix compile warn after 1807a08e
New enum to add to switch so compiler doesn't complain.

   commit 1807a08e4f
   Author:     Ilia Mirkin <imirkin@alum.mit.edu>
   AuthorDate: Thu Aug 27 23:05:03 2015 -0400
   Commit:     Ilia Mirkin <imirkin@alum.mit.edu>
   CommitDate: Thu Sep 10 17:38:33 2015 -0400

       nir: add nir_texop_texture_samples and convert from glsl

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2015-09-13 11:31:45 -04:00
Rob Clark
bf45a7d28e freedreno/ir3: fix compile break after a4aa25be
Following commit dropped the unused memctx arg:

   commit a4aa25be1e
   Author:     Jason Ekstrand <jason.ekstrand@intel.com>
   AuthorDate: Wed Sep 9 13:24:35 2015 -0700
   Commit:     Jason Ekstrand <jason.ekstrand@intel.com>
   CommitDate: Fri Sep 11 09:21:20 2015 -0700

       nir: Remove the mem_ctx parameter from ssa_def_rewrite_uses

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2015-09-13 11:31:30 -04:00